Module Stop Control Register C (Mstpcrc) - Renesas RX100 Series User Manual

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Module Stop Control Register C (MSTPCRC)

Address(es): 0008 0018h

Value after reset:

Value after reset:

b18 to b16 —

b30 to b20 —

Set the PRCR.PRC1 bit to 1 (write enabled) before rewriting this register.

Note 1. The corresponding MSTPC0 bit should not be set to 1 during access to the RAM. The corresponding RAM should not be

accessed while the MSTPC0 bit is 1.

Note 2. The MSTPC19 bit should be rewritten while the oscillation of the clock to be controlled by this bit is stable. For entering software

standby mode after rewriting this bit, wait for two cycles of the slowest clock among the clocks output by the oscillators actually

oscillating and execute the WAIT instruction.

DSLPE Bit (Deep Sleep Mode Enable)

The DSLPE bit enables or disables a transition to deep sleep mode.

When the CPU executes the WAIT instruction with the DSLPE bit set to 1 and the SBYCR.SSBY and

MSTPCRA.MSTPA28 bits meet specified conditions, the MCU enters deep sleep mode. For details, refer to section

11.6.2, Deep Sleep Mode .

R01UH0822EJ0100 Rev.1.00

Jul 31, 2019

RAM0 Module Stop*

Clock Frequency Accuracy

Measurement Circuit Module

Deep Sleep Mode Enable

Target module: RAM0 (0000 0000h to 0000 2FFFh)

0: RAM0 operating

1: RAM0 stopped

These bits are read as 0. The write value should be 0.

These bits are read as 1. The write value should be 1.

Target module: CAC

0: This module clock is enabled

1: This module clock is disabled

These bits are read as 1. The write value should be 1.

0: Deep sleep mode is disabled

1: Deep sleep mode is enabled

11. Low Power Consumption

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