Renesas RX100 Series User Manual page 376

RX13T Group
NFCS[1:0] Bits (Noise Filter Clock Select)
These bits set the sampling interval for the noise filters. When setting the NFCS[1:0] bits, wait for two cycles of the
selected sampling interval before setting the input-capture function. When the NFCS[1:0] bits are set to 11b, i.e.
selecting the external clock as the source to drive counting, wait for two cycles of the external clock before setting the
input capture function.
 MTU0.NFCRC
Address(es): MTU0.NFCRC 0009 5299h
b7 b6
— —
Value after reset: 0 0
Bit Symbol Bit Name
b0 NFAEN Noise Filter A Enable
b1 NFBEN Noise Filter B Enable
b2 NFCEN Noise Filter C Enable
b3 NFDEN Noise Filter D Enable
b5, b4 NFCS[1:0] Noise Filter Clock Select
b7, b6 — Reserved
The NFCRC register sets the noise filter function of external clock pins common to each channel.
NFAEN Bit (Noise Filter A Enable)
This bit disables or enables the noise filter for input from the MTCLKA pin. Since changing the value of the bit may lead
to the internal generation of an unexpected edge, do so after stopping the internal counter.
NFBEN Bit (Noise Filter B Enable)
This bit disables or enables the noise filter for input from the MTCLKB pin. Since changing the value of the bit may lead
to the internal generation of an unexpected edge, do so after stopping the internal counter.
NFCEN Bit (Noise Filter C Enable)
This bit disables or enables the noise filter for input from the MTCLKC pin. Since changing the value of the bit may lead
to the internal generation of an unexpected edge, do so after stopping the internal counter.
NFDEN Bit (Noise Filter D Enable)
This bit disables or enables the noise filter for input from the MTCLKD pin. Since changing the value of the bit may lead
to the internal generation of an unexpected edge, do so after stopping the internal counter.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
NFCS[1:0] NFDEN NFCEN NFBEN NFAEN
0 0 0 0
19. Multi-Function Timer Pulse Unit 3 (MTU3c)
b1 b0
0 0
Description
0: The noise filter for the MTCLKA pin is disabled.
1: The noise filter for the MTCLKA pin is enabled.
0: The noise filter for the MTCLKB pin is disabled.
1: The noise filter for the MTCLKB pin is enabled.
0: The noise filter for the MTCLKC pin is disabled.
1: The noise filter for the MTCLKC pin is enabled.
0: The noise filter for the MTCLKD pin is disabled.
1: The noise filter for the MTCLKD pin is enabled.
b5 b4
0 0: PCLKB/1
0 1: PCLKB/2
1 0: PCLKB/8
1 1: PCLKB/32
These bits are read as 0. The write value should be 0.
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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