Bit Rate Register (Brr) - Renesas RX100 Series User Manual

RX13T Group
23.2.11

Bit Rate Register (BRR)

Address(es): SCI1.BRR 0008 A021h, SCI5.BRR 0008 A0A1h, SCI12.BRR 0008 B301h
b7 b6
Value after reset: 1 1
The BRR register is an 8-bit register that adjusts the bit rate.
As each SCI channel has independent baud rate generator control, different bit rates can be set for each. Table 23.10
shows the relationship between the setting (N) in the BRR register and the bit rate (B) for normal asynchronous mode,
multi-processor communication, clock synchronous mode, smart card interface mode, simple SPI mode, and simple I
mode.
The BRR register is writable only when the TE and RE bits in the SCR register are 0.
Table 23.10 Relationship between N Setting in BRR Register and Bit Rate B
SEMR Settings
Mode BGDM bit
Asynchronous, 0
multi-processor
communication
0
1
1
Clock synchronous, simple SPI
Smart card interface
2 1
Simple I C*
B: Bit rate (bps)
BRR setting for on-chip baud rate generator (0  N 255)
N:
PCLK: Operating frequency (MHz)
n and S: Determined by the settings of the SMR and SCMR registers as listed in Table 23.12 and Table 23.13.
Note 1. Adjust the bit rate so that the widths at high and low level of the SCL output in simple I
Table 23.11 Calculating Widths at High and Low Level for SCL
Mode SCL
2
I C High period (minimum value)
Low period (minimum value)
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
1 1 1 1
ABCS bit BRR Setting
0

PCLK 10
N = -------------------------------------- - 1
2n 1 –

64 2
1

PCLK 10
N = -------------------------------------- - 1
2n 1 –

32 2
0
1

PCLK 10
N = -------------------------------------- - 1
2n 1
–

16 2

PCLK 10
N ----------------------------------- 1
=
2n 1 –
 
8 2

PCLK 10
N ------------------------------------ 1
=
2n + 1

S 2

PCLK 10
N = -------------------------------------- - 1
2n 1 –

64 2
Formula (Result in Seconds)
  4 
N + 1
  4 
N + 1
23. Serial Communications Interface (SCIg, SCIh)
b1 b0
1 1
Error (%)
6

–
Error =


B 
6

–
Error =


B

6

–
Error =


B

6
–
B
6

–
Error =


B

6
–

B
1
2n 1
–
   --------------------------------
2 7
6

PCLK 10
1
2n 1 –
  
--------------------------------
2 8
6

PCLK 10
6 

PCLK 10
--------------------------------------------------------------- - 1 –

2n 1 –

    
B 64 2 N + 1
6


PCLK 10
--------------------------------------------------------------- - 1 –

2n 1 –

    
B 32 2 N + 1
6


PCLK 10
--------------------------------------------------------------- - 1 –

2n 1 –
     
B 16 2 N + 1
6


PCLK 10

------------------------------------------------------------- - 1 –

2n + 1

    
B S 2 N 1
+
2 2
C mode satisfy the I C-bus standard.
Page 606 of 1041
2
C

100

100

100
100