Clock; Double-Speed Mode - Renesas RX100 Series User Manual

RX13T Group
23.3.3

Clock

Either an internal clock generated by the on-chip baud rate generator or an external clock input to the SCKn pin can be
selected as the SCI's transfer clock, according to the setting of the CM bit in the SMR register and the CKE[1:0] bits in
the SCR register.
When an external clock is input to the SCKn pin, the clock frequency should be 16 times the bit rate (when SEMR.ABCS
bit = 0) and 8 times the bit rate (when SEMR.ABCS bit = 1). In addition, when an external clock is specified, the base
clock of MTIOC1A and MTIOC2A can be selected by the SCIn.SEMR.ACS0 bit (n = 1, 5, 12).
When the SCI is operated on an internal clock, the clock can be output from the SCKn pin. The frequency of the clock
output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the
transmit data, as shown in Figure 23.6 .
SCKn
TXDn
0
Figure 23.6 Phase Relationship between Output Clock and Transmit Data
(Asynchronous Mode: SMR.CHR = 0, PE = 1, MP = 0, STOP = 1)
23.3.4

Double-Speed Mode

The output clock frequency of the on-chip baud rate generator is doubled by setting the SEMR.BGDM bit to 1, enabling
high-speed communication at a doubled bit rate. If the SEMR.ABCS bit is set to 1 under the above condition, the number
of base clock cycles changes from 16 to 8, so the bit rate becomes four times faster than the initial state.
As shown by Formula (1) in section 23.3.2, Receive Data Sampling Timing and Reception Margin in
Asynchronous Mode , setting the SEMR.ABCS bit to 1 changes the number of cycles to 8, and the sampling interval
becomes longer. This causes the reception margin to decrease. Therefore, setting the SEMR.BGDM bit to 1 and the
SEMR.ABCS bit to 0 is recommended instead of setting the SEMR.BGDM bit to 0 and the SEMR.ABCS bit to 1 for
high-speed operation at a doubled bit rate.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
D0 D1 D2 D3
23. Serial Communications Interface (SCIg, SCIh)
D4 D5 D6 D7 0/1
1 frame
1 1
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