Renesas RX100 Series User Manual page 20

22.4.1 Refresh Operations ................................................................................................................... 581
22.4.2 Clock Divide Ratio Setting ....................................................................................................... 581
23. Serial Communications Interface (SCIg, SCIh) ............................................................................ 582
23.1 Overview ........................................................................................................................................... 582
23.2 Register Descriptions ......................................................................................................................... 588
23.2.1 Receive Shift Register (RSR) ................................................................................................... 588
23.2.2 Receive Data Register (RDR) ................................................................................................... 588
23.2.3 Receive Data Register H, L, HL (RDRH, RDRL, RDRHL) .................................................... 589
23.2.4 Transmit Data Register (TDR) ................................................................................................. 589
23.2.5 Transmit Data Register H, L, HL (TDRH, TDRL, TDRHL) ................................................... 590
23.2.6 Transmit Shift Register (TSR) .................................................................................................. 590
23.2.7 Serial Mode Register (SMR) .................................................................................................... 591
23.2.8 Serial Control Register (SCR) .................................................................................................. 595
23.2.9 Serial Status Register (SSR) ..................................................................................................... 599
23.2.10 Smart Card Mode Register (SCMR) ........................................................................................ 604
23.2.11 Bit Rate Register (BRR) ........................................................................................................... 606
23.2.12 Modulation Duty Register (MDDR) ......................................................................................... 614
23.2.13 Serial Extended Mode Register (SEMR) .................................................................................. 615
23.2.14 Noise Filter Setting Register (SNFR) ....................................................................................... 618
2
23.2.15 I C Mode Register 1 (SIMR1) ................................................................................................. 619
2
23.2.16 I C Mode Register 2 (SIMR2) ................................................................................................. 620
2
23.2.17 I C Mode Register 3 (SIMR3) ................................................................................................. 621
2
23.2.18 I C Status Register (SISR) ....................................................................................................... 623
23.2.19 SPI Mode Register (SPMR) ..................................................................................................... 624
23.2.20 Extended Serial Module Enable Register (ESMER) ................................................................ 625
23.2.21 Control Register 0 (CR0) .......................................................................................................... 626
23.2.22 Control Register 1 (CR1) .......................................................................................................... 626
23.2.23 Control Register 2 (CR2) .......................................................................................................... 627
23.2.24 Control Register 3 (CR3) .......................................................................................................... 628
23.2.25 Port Control Register (PCR) ..................................................................................................... 628
23.2.26 Interrupt Control Register (ICR) .............................................................................................. 629
23.2.27 Status Register (STR) ............................................................................................................... 630
23.2.28 Status Clear Register (STCR) ................................................................................................... 631
23.2.29 Control Field 0 Data Register (CF0DR) ................................................................................... 631
23.2.30 Control Field 0 Compare Enable Register (CF0CR) ................................................................ 632
23.2.31 Control Field 0 Receive Data Register (CF0RR) ..................................................................... 632
23.2.32 Primary Control Field 1 Data Register (PCF1DR) ................................................................... 632
23.2.33 Secondary Control Field 1 Data Register (SCF1DR) ............................................................... 633
23.2.34 Control Field 1 Compare Enable Register (CF1CR) ................................................................ 633
23.2.35 Control Field 1 Receive Data Register (CF1RR) ..................................................................... 633
23.2.36 Timer Control Register (TCR) ................................................................................................. 634