Renesas RX100 Series User Manual page 766

RX13T Group
7 8 9 1
SCL0
ACK
SDA0 b1 b0 b7
DATA n-2
BBSY
MST
TRS
TDRE
Receive data (DATA n-2)
TEND
RDRF
ICDRT
DATA n-2
ICDRS
ICDRR DATA n-3
ACKBT
0 (ACK)
ACKBR
STOP
SP
WAIT
Write 1 to
WAIT bit
Figure 24.14 Master Receive Operation Timing (3) (When RDRFS bit is 0)
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Automatic low hold (WAIT)
2 3 4 5 6 7
b6 b5 b4 b3 b2 b1
DATA n-1
Receive data (DATA n-1)
XXXX (last data for transmission
[7-bit addresses + R/Upper 10 bits + R])
DATA n-1
DATA n-2
0 (ACK)
0 (ACK)
Read ICDRR
register (DATA n-2)
[5]
8 9 1 2 3 4
ACK
b0 b7 b6 b5 b4
DATA n
DATA n-1
0 (ACK)
Read ICDRR
Write 1 to
register
ACKBT bit
(DATA n-1)
[6]
2
24. I C-bus Interface (RIICa)
Automatic low hold (WAIT)
5 6 7 8 9
NACK
b3 b2 b1 b0
Receive data (DATA n)
DATA n
DATA n
1 (NACK)
1 (NACK)
Read ICDRR register
Write 1 Set WAIT
(last data for reception
to SP bit bit to 0
[DATA n])
[7]
Page 766 of 1041
P
0
Clear
STOP flag
[9]