Flash Processing Start Address Register H (Fsarh); Flash Processing Start Address Register L (Fsarl) - Renesas RX100 Series User Manual

RX13T Group
Writing to the extra area is started by writing 1 to the OPST bit. Do not write to the CMD[2:0] bits while a software
command is being executed.
31.4.11

Flash Processing Start Address Register H (FSARH)

Address(es): FLASH.FSARH 007F FF84h
b7 b6
— —
Value after reset: 0 0
The FSARH register is used to set the target processing address or the start address of the target processing range in the
flash memory when a software command is executed.
Set bit 19 to bit 16 of the flash memory address for programming/erasure in this register.
Data can be written to this register in ROM P/E mode or E2 DataFlash P/E mode.
This register is initialized by a reset or setting the FRESETR.FRESET bit to 1. Data cannot be written to this register
while the FRESETR.FRESET bit is 1.
If this register is read while executing a software command set by the FEXCR register, an undefined value is read.
Refer to Figure 31.1 and Figure 31.2 for details on the addresses of the flash memory.
31.4.12

Flash Processing Start Address Register L (FSARL)

Address(es): FLASH.FSARL 007F FF82h
b15 b14
0 0
Value after reset:
The FSARL register is used to set the target processing address or the start address of the target processing range in the
flash memory when a software command is executed.
Set bit 15 to bit 0 of the flash memory address for programming/erasure in this register.
When the target is the ROM, set bit 1 and bit 0 to 00b.
Data can be written to this register in ROM P/E mode or E2 DataFlash P/E mode.
This register is initialized by a reset or setting the FRESETR.FRESET bit to 1. Data cannot be written to this register
while the FRESETR.FRESET bit is 1.
If this register is read while executing a software command set by the FEXCR register, an undefined value is read.
Refer to Figure 31.1 and Figure 31.2 for details on the addresses of the flash memory.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
— —
0 0 0 0
b13 b12 b11 b10
0 0 0 0
b1 b0
0 0
b9 b8 b7 b6
0 0 0 0
31. Flash Memory (FLASH)
b5 b4 b3 b2
0 0 0 0
Page 920 of 1041
b1 b0
0 0