Basic Operation (With Channel-Dedicated Sample-And-Hold Circuits) - Renesas RX100 Series User Manual

RX13T Group
26.3.3.2

Basic Operation (With Channel-Dedicated Sample-and-Hold Circuits)

When a channel-dedicated sample-and-hold circuit is used, sample-and-hold operations are performed first, after which
the analog inputs on all selected channels are A/D converted as below. The channels for which the channel-dedicated
sample-and-hold circuits are to be used can be selected by the ADSHCR.SHANS[2:0] bits.
In continuous scan mode, the internal reference voltage A/D conversion select bit (S12AD.ADEXICR.OCSA) should be
set to 0 (deselected).
(1) Analog input sampling of all channels for which the channel-dedicated sample-and-hold circuits are to be used is
started when the ADCSR.ADST bit is set to 1 (A/D conversion start) by software, synchronous trigger input, or
asynchronous trigger input.
(2) After sample-and-hold operation, A/D conversion is performed for ANn channels selected by the ADANSA0
register, starting from the channel with the smallest number n.
(3) Each time A/D conversion of a single channel is completed, the result of A/D conversion is stored in the
corresponding A/D data register (ADDRy).
(4) When A/D conversion of all the selected channels is completed, a scan end interrupt request is generated if the
ADCSR.ADIE bit is 1 (interrupt generation upon scanning completion enabled). At the same time, analog input
sampling is started for all the channels for which the channel-dedicated sample-and-hold circuits are to be used.
(5) The ADCSR.ADST bit is not automatically cleared and steps 2 to 4 are repeated as long as the bit remains 1. When
the ADCSR.ADST bit is set to 0 (A/D conversion stop), A/D conversion stops and the 12-bit A/D converter enters a
wait state.
(6) When the ADCSR.ADST bit is then set to 1 (A/D conversion start), analog input sampling is started again for all the
channels for which the channel-dedicated sample-and-hold circuits are to be used.
A/D conversion
ADST
started
Sample-and-hold time
Channel 0
Waiting for conversion
(AN000)
Channel 1
Waiting for conversion
(AN001)
ADDR0
ADDR1
Scan end
interrupt
Note 1. indicates the instruction is executed by software.
Note 2. The converted data of A/D conversion 4 is ignored.
Figure 26.10 Example of Operation in Continuous Scan Mode
(Channel-Dedicated Sample-and-Hold Circuits Used)
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Sampling-and-holding and scanning repeated
*1
Set
(1)
A/D conversion
time
Sampling
Holding
A/D conversion 1
(2)
Sampling Holding
Stored
Waiting for
Sampling Holding
conversion
A/D conversion 2 Sampling
(3)
A/D conversion result 1
Stored (3)
A/D conversion result 2
(4)
Interrupt generated
26. 12-Bit A/D Converter (S12ADF)
Cleared
(5)
A /D conversion 3 Waiting for conversion
(2)
Waiting for
Holding *2
A/D conversion 4
conversion
(3)
Stored
A/D conversion result 3
Page 848 of 1041
Set
(6)
Sampling
Sampling