Input Level Control/Status Register 4 (Icsr4) - Renesas RX100 Series User Manual

RX13T Group
For details, refer to section 20.3.7, Recover from High-Impedance State .
20.2.3

Input Level Control/Status Register 4 (ICSR4)

Address(es): POE.ICSR4 0008 C4D6h
b15 b14
— —
0 0
Value after reset:
Bit Symbol
b1, b0 POE10M[1:0]
b7 to b2 —
b8 PIE4
b9 POE10E
b11, b10 —
b12 POE10F
b15 to b13 —
Note 1. Can be modified only once after a reset.
Note 2. Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
The ICSR4 register selects the POE10# pin input mode, controls the enable/disable of interrupts, and indicates status.
POE10M[1:0] Bits (POE10 Mode Select)
These bits select the input mode of the POE10# pin.
PIE4 Bit (Port Interrupt Enable 4)
This bit enables or disables interrupt requests when the POE10F flag is set to 1.
POE10E Bit (POE10 High-Impedance Enable)
This bit specifies whether to put the output of the corresponding pin in the high-impedance state when the POE10F flag
is set to 1.
POE10F Flag (POE10 Flag)
This flag indicates that a high-impedance request has been input to the POE10# pin.
[Setting condition]
 When the input set by the POE10M[1:0] bits occurs at the POE10# pin
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b13 b12 b11 b10
POE10
— — —
F
0 0 0 0
Bit Name
POE10 Mode Select
Reserved
Port Interrupt Enable 4
POE10 High-Impedance
Enable
Reserved
POE10 Flag
Reserved
b9 b8 b7 b6
POE10
PIE4 — —
E
0 0 0 0
Description
b1 b0
0 0: Accepts a request on the falling edge of POE10# pin input.
0 1: Accepts a request when POE10# pin input has been sampled
16 times at PCLK/8 clock pulses and all are low level.
1 0: Accepts a request when POE10# pin input has been sampled
16 times at PCLK/16 clock pulses and all are low level.
1 1: Accepts a request when POE10# pin input has been sampled
16 times at PCLK/128 clock pulses and all are low level.
These bits are read as 0. The write value should be 0.
0: Interrupt requests disabled
1: Interrupt requests enabled
0: Does not put the output in the high-impedance state by POE10#
signal.
1: Put the output in the high-impedance state by POE10# signal.
These bits are read as 0. The write value should be 0.
0: Indicates that a high-impedance request has not been input to
the POE10# pin.
1: Indicates that a high-impedance request has been input to the
POE10# pin.
These bits are read as 0. The write value should be 0.
20. Port Output Enable 3 (POE3C)
b5 b4 b3 b2
— — — —
0 0 0 0
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b1 b0
POE10M[1:0]
0 0
R/W
1
R/W*
R/W
R/W
1
R/W*
R/W
R/(W)
2
*
R/W