Renesas RX100 Series User Manual page 762

RX13T Group
Because the ICSR2.NACKF flag being 1 at this time indicates that no slave device recognized the address or there
was an error in communications, write 1 to the ICCR2.SP bit to issue a stop condition.
For master reception from a device with a 10-bit address, start by using master transmission to issue the 10-bit
address, and then issue a restart condition. After that, transmitting 1111 0b, the two higher-order bits of the slave
address, and the R bit places the RIIC in master receive mode.
(4) Dummy read the ICDRR register after confirming that the ICSR2.RDRF flag is 1; this makes the RIIC start output
of the SCL clock and start data reception.
(5) After 1 byte of data has been received, the ICSR2.RDRF flag is set to 1 on the rising edge of the eighth or ninth
cycle of SCL clock (the clock signal) as selected by the ICMR3.RDRFS bit. Reading the ICDRR register at this
time will produce the received data, and the RDRF flag is automatically set to 0 at the same time. Furthermore, the
value of the acknowledgment field received during the ninth cycle of SCL clock is returned as the value set in the
ICMR3.ACKBT bit. Furthermore, if the next byte to be received is the next to last byte, set the ICMR3.WAIT bit to
1 (for wait insertion) before reading the ICDRR register (containing the second byte from last). As well as enabling
NACK output even in the case of delays in processing to set the ICMR3.ACKBT bit to 1 (NACK) in step (6), due to
other interrupts, etc., this fixes the SCL0 line to the low level on the falling edge of the ninth clock cycle in
reception of the last byte, so the state is such that issuing a stop condition is possible.
(6) When the ICMR3.RDRFS bit is 0 and the slave device must be notified that it is to end transfer for data reception
after transfer of the next (final) byte, set the ICMR3.ACKBT bit to 1 (NACK).
(7) After reading the byte before last from the ICDRR register, if the value of the ICSR2.RDRF flag is confirmed to be
1, write 1 to the ICCR2.SP bit (stop condition issuance request) and then read the last byte from the ICDRR register.
When the ICDRR register is read, the RIIC is released from the wait state and issues the stop condition after low-
level output in the ninth clock cycle is completed or the SCL0 line is released from the low-hold state.
(8) Upon detecting the stop condition, the RIIC automatically sets bits MST and TRS in the ICCR2 register to 00b and
enters slave receive mode. Furthermore, detection of the stop condition leads to setting of the ICSR2.STOP flag to
1.
(9) After checking that the ICSR2.STOP flag is 1, set the ICSR2.NACKF and STOP flags to 0 for the next transfer
operation.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
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24. I C-bus Interface (RIICa)
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