Sda Output Delay Function - Renesas RX100 Series User Manual

RX13T Group
24.5

SDA Output Delay Function

The RIIC module incorporates a function for delaying output on the SDA line. The delay can be applied to all output
(issuing of the start, restart, and stop conditions, data, and the ACK and NACK signals) on the SDA line.
With the SDA output delay function, SDA output is delayed from detection of a falling edge of the SCL signal to ensure
that the SDA signal is output within the interval over which the SCL clock is at the low level. Doing this leads to usage
with the aim of preventing erroneous operation of communications devices, with the aim of satisfying the 300-ns (min.)
data-hold time requirement of the SMBus specification.
The output delay function is enabled by setting the ICMR2.SDDL[2:0] bits to any value other than 000b, and disabled by
setting the same bits to 000b.
While the SDA output delay function is enabled (i.e. while the ICMR2.SDDL[2:0] bits are set to any value other than
000b), the ICMR2.DLCS bit selects the clock source for counting by the SDA output delay counter as the internal base
clock (IICφ) for the RIIC module or as a clock signal derived by dividing the frequency of the internal base clock by two
(IICφ/2). The counter counts the number of cycles set in the ICMR2.SDDL[2:0] bits. After counting of the set number of
cycles of delay is completed, the RIIC module places the required output (start, restart, or stop condition, data, or an
ACK or NACK signal) on the SDA line.
Transmit mode
S
SCL0
SDA0
Receive mode
1 to 7
SCL0
SDA0
b7 to b1
Master mode
ICBRH ICBRL
SCL0 ST
SDA0
1
*
BBSY
ST
Figure 24.22 SDA Output Delay Function
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
Analog noise filter delay time + PCLK sampling error (1 PCLK (max))
Digital noise filter delay time (NFE bit, NF[1:0] bits settings = 0.5 PCLK (min), 1 IIC to 4 IIC (max))
SDA output delay time (DLCS bit, SDDL[2:0] bits settings = 0 (min) to 14 IIC (max))
b7 to b1
SDA output delay
8
b0
SDA output delay
ICBRH ICBRL
1 2 to 8
b7 b6 to b0 ACK/NACK
SDA output delay
8
b0
9
ACK/NACK
ICBRL ICBRH
9 RS
1
*
Note 1. The output delay function is set by the DLCS and SDDL[2:0] bits when a start (ST),
restart (RS), or stop (SP) condition is issued.
2
24. I C-bus Interface (RIICa)
SDA output release timing
9
ACK/NACK
SDA output release timing
ICBRH
ICBRL
1 to 9 SP
1
*
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ICBRL