Function To Prevent Failure To Receive Data - Renesas RX100 Series User Manual

RX13T Group
24.8.3

Function to Prevent Failure to Receive Data

If response processing is delayed when receive data (ICDRR) read is delayed for a period of one transfer byte or more
with receive data full (ICSR2.RDRF flag is 1) in receive mode (ICCR2.TRS bit is 0), the RIIC holds the SCL0 line low
automatically immediately before the next data is received to prevent failure to receive data.
This function to prevent failure to receive data using the automatic low-hold function is also enabled even if the read
processing of the final receive data is delayed and, in the meantime, the RIIC's own slave address is designated after a
stop condition is issued. This function does not disturb other communication because the RIIC does not hold the SCL0
line low when a mismatch with its own slave address occurs after a stop condition is issued.
Sections in which the SCL0 line is held low can be selected with a combination of the WAIT and RDRFS bits in the
ICMR3 register.
(1) 1-Byte Receive Operation and Automatic Low-Hold Function Using the WAIT Bit
When the ICMR3.WAIT bit is set to 1, the RIIC performs 1-byte receive operation using the WAIT bit function.
Furthermore, when the ICMR3.RDRFS bit is 0, the RIIC automatically sends the ICMR3.ACKBT bit value for the
acknowledge bit in the period from the falling edge of the eighth SCL clock cycle to the falling edge of the ninth SCL
clock cycle, and automatically holds the SCL0 line low at the falling edge of the ninth SCL clock cycle using the WAIT
bit function. This low-hold is released by reading data from the ICDRR register, which enables bytewise receive
operation.
The WAIT bit function is enabled for receive bytes after a match with the RIIC's own slave address (including the
general call address and host address) is obtained in master receive mode or slave receive mode.
(2) 1-Byte Receive Operation (ACK/NACK Transmission Control) and Automatic Low-Hold
Function Using the RDRFS Bit
When the ICMR3.RDRFS bit is set to 1, the RIIC performs 1-byte receive operation using the RDRFS bit function.
When the RDRFS bit is set to 1, the ICSR2.RDRF flag (receive data full) is set to 1 at the rising edge of the eighth SCL
clock cycle, and the SCL0 line is automatically held low at the falling edge of the eighth SCL clock cycle. This low-hold
is released by writing a value to the ICMR3.ACKBT bit, but cannot be released by reading data from the ICDRR register,
which enables receive operation by the ACK/NACK transmission control according to the data received in byte units.
The RDRFS bit function is enabled for receive bytes after a match with the RIIC's own slave address (including the
general call address and host address) is obtained in master receive mode or slave receive mode.
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
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24. I C-bus Interface (RIICa)
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