Port Input Data Register (Pidr) - Renesas RX100 Series User Manual

RX13T Group
17.3.3

Port Input Data Register (PIDR)

Address(es): PORT1.PIDR 0008 C041h, PORT2.PIDR 0008 C042h, PORT3.PIDR 0008 C043h, PORT4.PIDR 0008 C044h,
PORT7.PIDR 0008 C047h, PORT9.PIDR 0008 C049h, PORTA.PIDR 0008 C04Ah, PORTB.PIDR 0008 C04Bh,
PORTD.PIDR 0008 C04Dh, PORTE.PIDR 0008 C04Eh
b7 b6
B7 B6
x x
Value after reset:
x: Undefined
Bit Symbol
b0 B0
b1 B1
b2 B2
b3 B3
b4 B4
b5 B5
b6 B6
b7 B7
m = 1 to 4, 7, 9, A, B, D, E
PIDR indicates individual pin states of port m.
The pin states of port m can be read with the PORTm.PIDR, regardless of the values of PORTm.PDR and PORTm.PMR.
The NMI pin state is reflected in the PE2 bit.
The bit corresponding to a pin that does not exist is reserved. A reserved bit is read as undefined, and cannot be modified.
Note: When using P36 and P37 as general I/O ports, set the MOSCCR.MOSTP bit to 1 (main clock oscillator is
stopped) and the P36 and P37 control bits in the PORT3.PMR register to 0 (use pin as general I/O port).
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
B5 B4 B3 B2
x x x x
Bit Name
Pm0
Pm1
Pm2
Pm3
Pm4
Pm5
Pm6
Pm7
b1 b0
B1 B0
x x
Description
Indicates individual pin states of the
corresponding port.
17. I/O Ports
R/W
R
R
R
R
R
R
R
R
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