Irq Control Register I (Irqcri) (I = 0 To 5) - Renesas RX100 Series User Manual

RX13T Group
14.2.7

IRQ Control Register i (IRQCRi) (i = 0 to 5)

Address(es): ICU.IRQCR0 0008 7500h to ICU.IRQCR5 0008 7505h
b7 b6
— —
Value after reset: 0 0
Bit Symbol
b1, b0 —
b3, b2 IRQMD[1:0]
b7 to b4 —
Only change the settings of this register while the corresponding interrupt request enable bit is prohibiting the interrupt
request (IENj bit in IERm (m = 02h to 1Fh, j = 0 to 7) is 0). After changing the setting, clear the IR flag in IRn before
setting the interrupt enable bit. However, when the change is to the low level, the IR flag does not require clearing.
IRQMD[1:0] Bits (IRQ Detection Sense Select)
These bits select the interrupt detection sensing method of IRQi pin.
For the external pin interrupt detection setting, see section 14.4.8, External Pin Interrupts .
R01UH0822EJ0100 Rev.1.00
Jul 31, 2019
b5 b4 b3 b2
— — IRQMD[1:0]
0 0 0 0
Bit Name Description
Reserved These bits are read as 0. The write value should be 0.
IRQ Detection Sense
b3 b2
0 0: Low level
Select
0 1: Falling edge
1 0: Rising edge
1 1: Rising and falling edges
Reserved These bits are read as 0. The write value should be 0.
b1 b0
— —
0 0
14. Interrupt Controller (ICUb)
R/W
R/W
R/W
R/W
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