Interrupt Operation; Dma Support - Renesas M16C/29 Series User Manual

M 1 6 C 2 / 9 G o r u p

13.2 Interrupt Operation

The IC/OC interrupt contains several request causes. Figure 13.18 shows the IC/OC interrupt block dia-
gram and Table 13.4 shows the IC/OC interrupt assignation.
When either the base timer reset request or base timer overflow request is generated, the IR bit in the BTIC
register corresponding to the IC/OC base timer interrupt is set to 1 (with an interrupt request). Also when an
interrupt request in each eight channels (channel i) is generated, the bit i in the G1IR register is set to 1 (with
an interrupt request). At this time, if the bit i in the G1IE0 register is 1 (IC/OC interrupt 0 request enabled),
the IR bit in the ICOC0IC register corresponding to the IC/OC interrupt 0 is set to 1 (with an interrupt
request). And if the bit i in the G1IE1 register is 1 (IC/OC interrupt 1 request enabled), the IR bit in the
ICOC1IC register corresponding to the IC/OC interrupt 1 is set to 1(with an interrupt request).
Additionally, because each bit in the G1IR register is not automatically set to 0 even if the interrupt is
acknowledged, set to 0 by program. If these bits are left as 1, all IC/OC channel interrupt causes, which are
generated after setting the IR bit to 1, will be disabled.
Figure 13.18 IC/OC Interrupt and DMA request generation
Table 13.4 Interrupt Assignment
Interrupt
IC/OC base timer interrupt
IC/OC interrupt 0
IC/OC interrupt 1

13.3 DMA Support

Each of the interrupt sources - the eight IC/OC channel interrupts and the one Base Timer interrupt - are
capable of generating a DMA request.
R e . v 1 1 . 2 M r a 3 . , 0 2 0 0 7
R E J 0 9 B 0 1 0 1 0 - 1 1 2
Interrupt control register
BTIC(0047
ICOC0IC(0045
ICOC0IC(0046
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f o 4 5 8
)
16
)
16
)
16
13. Timer S