Timer Interrupt And Tomn Pin Output At Operation Start - Renesas RL78/G1P Hardware User Manual

16-bit single-chip microcontroller

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6.6.5 Timer interrupt and TOmn pin output at operation start

In the interval timer mode or capture mode, the MDmn0 bit in timer mode register mn (TMRmn) sets whether or not to

generate a timer interrupt at count start.

When MDmn0 is set to 1, the count operation start timing can be known by the timer interrupt (INTTMmn) generation.

In the other modes, neither timer interrupt at count operation start nor TOmn output is controlled.

Figure 6-38 shows operation examples when the interval timer mode (TOEmn = 1, TOMmn = 0) is set.

Figure 6-38. Operation examples of timer interrupt at count operation start and TOmn output

When MDmn0 is set to 1, a timer interrupt (INTTMmn) is output at count operation start, and TOmn performs a toggle

When MDmn0 is set to 0, a timer interrupt (INTTMmn) is not output at count operation start, and TOmn does not

change either. After counting one cycle, INTTMmn is output and TOmn performs a toggle operation.

Remark m: Unit number (m = 0), n: Channel number (n = 0 to 3)

R01UH0895EJ0100 Rev.1.00

Nov 29, 2019

(a) When MDmn0 is set to 1

Count operation start

(b) When MDmn0 is set to 0

Count operation start

CHAPTER 6 TIMER ARRAY UNIT