Oscillation Stabilization Time Counter Status Register (Ostc) - Renesas RL78/G1P Hardware User Manual

RL78/G1P

5.3.4 Oscillation stabilization time counter status register (OSTC)

This is the register that indicates the count status of the X1 clock oscillation stabilization time counter.
The X1 clock oscillation stabilization time can be checked in the following case,
 If the X1 clock starts oscillation while the high-speed on-chip oscillator clock is being used as the CPU clock.
 If the STOP mode is entered and then released while the high-speed on-chip oscillator clock is being used as the
CPU clock with the X1 clock oscillating.
The OSTC register can be read by a 1-bit or 8-bit memory manipulation instruction.
When reset signal is generated, the STOP instruction and MSTOP (bit 7 of clock operation status control register
(CSC)) = 1 clear the OSTC register to 00H.
Remark The oscillation stabilization time counter starts counting in the following cases.
 When oscillation of the X1 clock starts (EXCLK = 0  MSTOP = 0)
 When the STOP mode is released
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
CHAPTER 5 CLOCK GENERATOR
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