Table of Contents
Advertisement
R8C/18 Group, R8C/19 Group
12.1.3
Special Interrupts
Special interrupts are non-maskable.
12.1.3.1
Watchdog Timer Interrupt
The watchdog timer interrupt is generated by the watchdog timer. Reset the watchdog timer after the
watchdog timer interrupt is generated. For details, refer to 13. Watchdog Timer.
12.1.3.2
Oscillation Stop Detection Interrupt
The oscillation stop detection interrupt is generated by the oscillation stop detection function. For
details of the oscillation stop detection function, refer to 10. Clock Generation Circuit.
12.1.3.3
Voltage Monitor 2 Interrupt
The voltage monitor 2 interrupt is generated by the voltage detection circuit. For details of the voltage
detection circuit, refer to 7. Voltage Detection Circuit.
12.1.3.4
Single-Step Interrupt, and Address Break Interrupt
Do not use these interrupts. They are for use by development tools only.
12.1.3.5
Address Match Interrupt
The address match interrupt is generated immediately before executing an instruction that is stored
at an address indicated by registers RMAD0 to RMAD1 when the AIER0 or AIER1 bit in the AIER
register is set to 1 (address match interrupt enable). For details of the address match interrupt, refer
to 12.4 Address Match Interrupt.
12.1.4
Peripheral Function Interrupt
The peripheral function interrupt is generated by the internal peripheral function of the MCU and is a
maskable interrupt. Refer to Table 12.2 Relocatable Vector Tables for sources of the peripheral
function interrupt. For details of peripheral functions, refer to the descriptions of individual peripheral
functions.
Rev.1.30
Apr 14, 2006
REJ09B0222-0130
Page 74 of 233
12. Interrupts
Advertisement
Table of Contents
