Noise Filter Enable Register 1 (Nfen1) - Renesas RL78/G1P Hardware User Manual

RL78/G1P

6.3.13 Noise filter enable register 1 (NFEN1)

The NFEN1 register is used to set whether the noise filter can be used for the timer input signal to each channel.
Enable the noise filter by setting the corresponding bits to 1 on the pins in need of noise removal.
When the noise filter is ON, match detection and synchronization of the 2 clocks is performed with the CPU/peripheral
hardware clock (f ). When the noise filter is OFF, only synchronization is performed with the CPU/peripheral hardware
MCK
clock (f ) .
Note
MCK
The NFEN1 register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Note For details, see 6.5.1 (2) When valid edge of input signal via the TImn pin is selected (CCSmn = 1) and
6.5.2 Start timing of counter.
Address: F0071H After reset: 00H
Symbol 7
NFEN1 0
TNFEN03
0
1
TNFEN02
0
1
TNFEN01
0
1
TNFEN00
0
1
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Figure 6-21. Format of Noise Filter Enable Register 1 (NFEN1)
R/W
6 5
0 0
Enable/disable using noise filter of TI03 pin input signal
Noise filter OFF
Noise filter ON
Enable/disable using noise filter of TI02 pin input signal
Noise filter OFF
Noise filter ON
Enable/disable using noise filter of TI01 pin input signal
Noise filter OFF
Noise filter ON
Enable/disable using noise filter of TI00 pin input signal
Noise filter OFF
Noise filter ON
CHAPTER 6 TIMER ARRAY UNIT
4 3
0 TNFEN03 TNFEN02
2 1
TNFEN01 TNFEN00
0
156