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16.5.7 Bit 6: Communication Mode Select Bit (Transfer Direction Select Bit: TRX)
This TRX bit decides a transfer direction for data communication. When the TRX bit is set to 0, receive
mode is entered and data is received from a transmit device. When the TRX bit is set to 1, transmit mode
is entered, and address data and control data are output to the SDA
ated in the SCL
MM
The TRX bit is set to 1 automatically in the following condition:
•In slave mode, when the ALS in the S1D0 register to 0(addressing format), the AAS flag is set to
1 (address match) after the address data is received, and the received R/W bit is set to 1
The TRX bit is set to 0 in one of the following conditions:
•When an arbitration lost is detected
•When a STOP condition is detected
•When a START condition is detected
•When a START condition is disabled by the START condition duplicate protect function
•When the MST bit in the S10 register is set to 0(slave mode) and a start condition is detected
•When the MST bit is set to 0 and the ACK non-return is detected
•When the ES0 bit is set to 0(I
•When the IHR bit in the S1D0 register is set to 1(reset)
16.5.8 Bit 7: Communication mode select bit (master/slave select bit: MST)
The MST bit selects either master mode or slave mode for data communication. When the MST bit is set
to 0, slave mode is entered and the START/STOP condition generated by a master device are received.
The data communication is synchronized with the clock generted by the master. When the MST bit is set
to 1, master mode is entered and the START/STOP condition is generated.
Additionally, clocks required for the data communication are generated on the SCL
The MST bit is set to 0 in one of the following conditions.
•After 1-byte data of a master whose arbtration is lost if arbitration lost is detected
•When a STOP condition is detected
•When a START condition is detected
•When a start condition is disabled by the START condition duplicate protect function
•When the IHR bit in the S1D0 register is set to 1(reset)
•When the ES0 bit is set to 0(I
NOTE:
1. START condition duplicate protect function:
When the START condition is generated, after confirming that the BB flag in the S1D0 register is
set to 0 (bus free), all the MST, TRX and BB flags are set to 1 at the same time. However, if the
BB flag is set to 1 immediately after the BB flag setting is confirmed because a START condition
is generated by other master device, bits MST and TRX cannot be written. The duplicate protect
function is valid from the rising edge of the BB flag until slave address is received. Refer to 16.9
START Condition Generation Method for details.
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16. MULTI-MASTER I
synchronized with a clock gener-
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C bus INTERFACE
(1)
(1)
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