Registers Controlling Clock Generator; Clock Operation Mode Control Register (Cmc) - Renesas RL78/G1P Hardware User Manual

RL78/G1P
Remark f : X1 clock oscillation frequency
X
f : High-speed on-chip oscillator clock frequency
IH
f : External main system clock frequency
EX
f : High-speed system clock frequency
MX
f : Main system clock frequency
MAIN
f : CPU/peripheral hardware clock frequency
CLK
f : Low-speed on-chip oscillator clock frequency
IL

5.3 Registers Controlling Clock Generator

The following nine registers are used to control the clock generator.
 Clock operation mode control register (CMC)
 System clock control register (CKC)
 Clock operation status control register (CSC)
 Oscillation stabilization time counter status register (OSTC)
 Oscillation stabilization time select register (OSTS)
 Peripheral enable registers 0, 1 (PER0, PER1)
 High-speed on-chip oscillator frequency select register (HOCODIV)
 High-speed on-chip oscillator trimming register (HIOTRM)
Caution Which registers and bits are included depends on the product. Be sure to set registers and bits that
are not mounted in a product to their initial values.

5.3.1 Clock operation mode control register (CMC)

This register is used to set the operation mode of the X1/P121 and X2/EXCLK/P122 pins, and to select a gain of the
oscillator.
The CMC register can be written only once by an 8-bit memory manipulation instruction after reset release. This
register can be read by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
CHAPTER 5 CLOCK GENERATOR
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