Timer Mode Register Mn (Tmrmn) - Renesas RL78/G1P Hardware User Manual

RL78/G1P

6.3.3 Timer mode register mn (TMRmn)

The TMRmn register sets an operation mode of channel n. This register is used to select the operation clock (f
select the count clock, select the master/slave, select the 16 or 8-bit timer (only for channels 1 and 3), specify the start
trigger and capture trigger, select the valid edge of the timer input, and specify the operation mode (interval, capture, event
counter, one-count, or capture and one-count).
Rewriting the TMRmn register is prohibited when the register is in operation (when TEmn = 1). However, bits 7 and 6
(CISmn1, CISmn0) can be rewritten even while the register is operating with some functions (when TEmn = 1) (for details,
see 6.8 Independent Channel Operation Function of Timer Array Unit and 6.9 Simultaneous Channel Operation
Function of Timer Array Unit.
The TMRmn register can be set by a 16-bit memory manipulation instruction.
Reset signal generation clears this register to 0000H.
Caution The bits mounted depend on the channels in the bit 11 of TMRmn register.
TMRm2, TMRm4, TMRm6: MASTERmn bit (n = 2)
TMRm1, TMRm3: SPLITmn bit (n = 1, 3)
TMRm0, TMRm5, TMRm7: Fixed to 0
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
CHAPTER 6 TIMER ARRAY UNIT
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MCK
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