Changing Interrupt Control Register Contents - Renesas R8C/18 Series Hardware Manual

R8C/18 Group, R8C/19 Group
12.5.6

Changing Interrupt Control Register Contents

(a) The contents of an interrupt control register can only be changed while no interrupt requests
corresponding to that register are generated. If interrupt requests may be generated, disable
interrupts before changing the interrupt control register contents.
(b) When changing the contents of an interrupt control register after disabling interrupts, be
careful to choose appropriate instructions.
Changing any bit other than IR bit
If an interrupt request corresponding to a register is generated while executing the instruction,
the IR bit may not be set to 1 (interrupt requested), and the interrupt request may be ignored.
If this causes a problem, use the following instructions to change the register: AND, OR,
BCLR, BSET
Changing IR bit
If the IR bit is set to 0 (interrupt not requested), it may not be set to 0 depending on the
instruction used. Therefore, use the MOV instruction to set the IR bit to 0.
(c) When disabling interrupts using the I flag, set the I flag as shown in the sample programs
below. Refer to (b) regarding changing the contents of interrupt control registers by the sample
programs.
Sample programs 1 to 3 are for preventing the I flag from being set to 1 (interrupts enabled) before
the interrupt control register is changed for reasons of the internal bus or the instruction queue buffer.
Example 1: Use NOP instructions to prevent I flag from being set to 1 before interrupt control
register is changed
INT_SWITCH1:
FCLR
AND.B
NOP
NOP
FSET
Example 2: Use dummy read to delay FSET instruction
INT_SWITCH2:
FCLR
AND.B
MOV.W MEM,R0
FSET
Example 3: Use POPC instruction to change I flag
INT_SWITCH3:
PUSHC FLG
FCLR
AND.B
POPC
Rev.1.30 Apr 14, 2006
REJ09B0222-0130
I ; Disable interrupts
#00H,0056H ; Set TXIC register to 00h
;
I ; Enable interrupts
I ; Disable interrupts
#00H,0056H ; Set TXIC register to 00h
; Dummy read
I ; Enable interrupts
I ; Disable interrupts
#00H,0056H ; Set TXIC register to 00h
FLG ; Enable interrupts
Page 96 of 233
12. Interrupts