R8C/18 Group, R8C/19 Group
7.1
VCC Input Voltage
7.1.1
Monitoring Vdet1
Vdet1 cannot be monitored.
7.1.2
Monitoring Vdet2
Set the VCA27 bit in the VCA2 register to 1 (voltage detection 2 circuit enabled). After td(E-A) has
elapsed (refer to 18. Electrical Characteristics), Vdet2 can be monitored by the VCA13 bit in the
VCA1 register.
7.1.3
Digital Filter
A digital filter can be used for monitoring the VCC input voltage. When the VW1C1 bit in the VW1C
register is set to 0 (digital filter enabled) for the voltage monitor 1 circuit and the VW2C1 bit in the
VW2C register is set to 0 (digital filter enabled) for the voltage monitor 2 circuit, the digital filter circuit
is enabled.
fRING-S divided by 1, 2, 4, or 8 may be selected as a sampling clock.
The level of VCC input voltage is sampled every sampling clock cycle, and when the sampled input
level matches two times, the internal reset signal changes to "L" or a voltage monitor 2 interrupt
request is generated.
Rev.1.30
Apr 14, 2006
REJ09B0222-0130
Page 46 of 233
7. Voltage Detection Circuit