System Clock Control Register (Ckc) - Renesas RL78/G1P Hardware User Manual

RL78/G1P

5.3.2 System clock control register (CKC)

This register is used to select a CPU/peripheral hardware clock and a main system clock.
The CKC register can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets this register to 00H.
Address: FFFA4H
Symbol 7
CKC 0
MCS
0
1
MCM0
0
1
Note Bit 5 is read-only.
Caution Be sure to set bits 0 to 3, 6, and 7 to "0".
Remark f
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Figure 5-3. Format of System Clock Control Register (CKC)
After reset: 00H R/W
Note
6 <5>
0 MCS
High-speed on-chip oscillator clock (f
High-speed system clock (f
Selects the high-speed on-chip oscillator clock (f
Selects the high-speed system clock (f
: High-speed on-chip oscillator clock frequency
IH
f : High-speed system clock frequency
MX
f : Main system clock frequency
MAIN
<4> 3
MCM0 0
Status of Main system clock (f
)
IH
)
MX
Main system clock (f ) operation control
MAIN
) as the main system clock (f
IH
) as the main system clock (f
MX
CHAPTER 5 CLOCK GENERATOR
2 1
0 0
)
MAIN
)
MAIN
)
MAIN
0
0
101