System Clock Control Register 0 (Cm0) - Renesas M16C/64A Series User Manual

M16C/64A Group
8.2.2

System Clock Control Register 0 (CM0)

System Clock Control Register 0
b7 b6 b5 b4 b3 b2 b1
Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting this register.
See Table 9.3 "Clock-Related Bit Setting and Modes" to select a clock and mode.
CM01 and CM00 (Clock output function select bit) (b1-b0)
The CLKOUT pin outputs can be selected. These bits are enabled when the PCLK5 bit in the PCLKR
register is set to 0 in single-chip mode. When the PCLK5 bit is 1, set bits CM01 and CM00 to 00b. Table
8.4 lists CLKOUT Pin Functions in Single-Chip Mode.
Table 8.4 CLKOUT Pin Functions in Single-Chip Mode
PCLKR Register
PCLK5 bit
0
0
0
0
1
Only set the combinations listed above.
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
b0
Symbol
CM0
Bit Symbol Bit Name
CM00
Clock output function select
bit (enabled in single-chip
mode only)
CM01
Wait mode peripheral
CM02
function clock stop bit
XCIN-XCOUT drive capacity
CM03
select bit
CM04 Port XC select bit
CM05 Main clock stop bit
Main clock division
CM06
select bit 0
CM07 System clock select bit
CM0 Register
CM01 bit CM00 bit
0
0
1
1
0
Address
0006h
b1 b0
0 0 : I/O port
0 1 : Output fC
1 0 : Output f8
1 1 : Output f32
0 : Peripheral function clock f1 does not
stop in wait mode
1 : Peripheral function clock f1 stops in
wait mode
0 : Low
1 : High
0 : I/O port
1 : XCIN-XCOUT oscillation function
0 : On
1 : Off
0 : Bits CM16 and CM17 in the CM1
register enabled
1 : Divide-by-8 mode
0 : Main clock, PLL clock, or on-chip
oscillator clock
1 : Sub clock
0
1
0
1
0
8. Clock Generator
Reset Value
0100 1000b
Function
CLKOUT Pin Output
I/O port
fC is output
f8 is output
f32 is output
f1 is output
Page 87 of 800
RW
RW
RW
RW
RW
RW
RW
RW