Notes On Interrupts; Reading Address 00000H; Sp Setting; External Interrupt And Key Input Interrupt - Renesas R8C/18 Series Hardware Manual

R8C/18 Group, R8C/19 Group
12.5

Notes on Interrupts

12.5.1

Reading Address 00000h

Do not read address 00000h by a program. When a maskable interrupt request is acknowledged, the
CPU reads interrupt information (interrupt number and interrupt request level) from 00000h in the
interrupt sequence. At this time, the acknowledged interrupt IR bit is set to 0.
If address 00000h is read by a program, the IR bit for the interrupt which has the highest priority
among the enabled interrupts is set to 0. This may cause the interrupt to be canceled, or an
unexpected interrupt to be generated.
12.5.2

SP Setting

Set any value in the SP before an interrupt is acknowledged. The SP is set to 0000h after reset.
Therefore, if an interrupt is acknowledged before setting a value in the SP, the program may run out
of control.
12.5.3

External Interrupt and Key Input Interrupt

Either "L" level or "H" level of at least 250 ns width is necessary for the signal input to pins INT0 to
INT3 and pins KI0 to KI3 regardless of the CPU clock.
12.5.4

Watchdog Timer Interrupt

Reset the watchdog timer after a watchdog timer interrupt is generated.
Rev.1.30 Apr 14, 2006
REJ09B0222-0130
Page 94 of 233
12. Interrupts