Timer Channel Enable Status Register M (Tem) - Renesas RL78/G1P Hardware User Manual

RL78/G1P

6.3.5 Timer channel enable status register m (TEm)

The TEm register is used to enable or stop the timer operation of each channel.
Each bit of the TEm register corresponds to each bit of the timer channel start register m (TSm) and the timer channel
stop register m (TTm). When a bit of the TSm register is set to 1, the corresponding bit of this register is set to 1. When a
bit of the TTm register is set to 1, the corresponding bit of this register is cleared to 0.
The TEm register can be read by a 16-bit memory manipulation instruction.
The lower 8 bits of the TEm register can be set with a 1-bit or 8-bit memory manipulation instruction with TEmL.
Reset signal generation clears this register to 0000H.
Figure 6-13. Format of Timer Channel Enable Status register m (TEm)
Address: F01B0H, F01B1H (TE0)
Symbol 15 14
TEm 0 0
TEH Indication of whether operation of the higher 8-bit timer is enabled or stopped when channel 3 is in the 8-bit
03
0 Operation is stopped.
1 Operation is enabled.
TEH Indication of whether operation of the higher 8-bit timer is enabled or stopped when channel 1 is in the 8-bit
01
0 Operation is stopped.
1 Operation is enabled.
TEmn
0 Operation is stopped.
1 Operation is enabled.
This bit displays whether operation of the lower 8-bit timer for TEm1 and TEm3 is enabled or stopped when channel
1 or 3 is in the 8-bit timer mode.
Remark m: Unit number (m = 0), n: Channel number (n = 0 to 3)
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
After reset: 0000H R
13 12 11 10
0 0 TEHm 0 TEHm
3
Indication of operation enable/stop status of channel n
9 8 7 6
0 0 0
1
timer mode
timer mode
CHAPTER 6 TIMER ARRAY UNIT
5 4 3 2
0 0 TEm TEm TEm
3 2
1 0
TEm
1 0
148