Peripheral Enable Register 0 (Per0) - Renesas RL78/G1P Hardware User Manual

16-bit single-chip microcontroller

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6.3.1 Peripheral enable register 0 (PER0)

The PER0 register is used to enable or disable supply of the clock signal to peripheral hardware. Clock supply to a

hardware that is not in use is stopped in order to reduce power consumption and noise.

When the timer array unit 0 is to be used, be sure to set bit 0 (TAU0EN) of this register to 1.

The PER0 register can be set by a 1-bit or 8-bit memory manipulation instruction.

Reset signal generation clears this register to 00H.

Address: F00F0H

After reset: 00H

Cautions 1. When setting the timer array unit, be sure to set the following registers first while the

2. Be sure to clear bits 1, 3, and 7 to "0".

R01UH0895EJ0100 Rev.1.00

Nov 29, 2019

Figure 6-9. Format of Peripheral Enable Register 0 (PER0)

Stops supply of input clock.

 SFR used by the timer array unit 0 cannot be written.

 The timer array unit 0 is in the reset status.

Supplies input clock.

 SFR used by the timer array unit 0 can be read/written.

TAUmEN bit is set to 1. If TAUmEN = 0, writing to a control register of timer array unit is

ignored, and all read values are default values (except for the timer input select register

0 (TIS0), input switch control register (ISC), noise filter enable register 1 (NFEN1), port

mode registers 1, 3 (PM1, PM3), and port registers 1, 3 ( P1, P3)).

 Timer status register mn (TSRmn)

 Timer channel enable status register m (TEm)

 Timer channel start register m (TSm)

 Timer channel stop register m (TTm)

 Timer output enable register m (TOEm)

 Timer output register m (TOm)

 Timer output level register m (TOLm)

 Timer output mode register m (TOMm)

Control of timer array 0 unit input clock

CHAPTER 6 TIMER ARRAY UNIT