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R8C/18 Group, R8C/19 Group
5.3
Voltage Monitor 1 Reset
A reset is applied using the on-chip voltage detection 1 circuit. The voltage detection 1 circuit monitors
the input voltage to the VCC pin. The voltage to monitor is Vdet1.
When the input voltage to the VCC pin reaches the Vdet1 level or below, the pins, CPU, and SFR are
reset.
When the input voltage to the VCC pin reaches the Vdet1 level or above, the low-speed on-chip
oscillator clock starts counting. When the low-speed on-chip oscillator clock count reaches 32, the
internal reset signal is held "H" and the MCU enters the reset sequence (refer to Figure 5.3). The low-
speed on-chip oscillator clock divided by 8 is automatically selected as the CPU after reset.
Refer to 4. Special Function Registers (SFRs) for the status of the SFR after voltage monitor 1 reset.
The internal RAM is not reset. When the input voltage to the VCC pin reaches the Vdet1 level or below
while writing to the internal RAM is in progress, the contents of internal RAM are undefined.
Refer to 7. Voltage Detection Circuit for details of voltage monitor 1 reset.
5.4
Voltage Monitor 2 Reset
A reset is applied using the on-chip voltage detection 2 circuit. The voltage detection 2 circuit monitors
the input voltage to the VCC pin. The voltage to monitor is Vdet2.
When the input voltage to the VCC pin reaches the Vdet2 level or below, pins, CPU, and SFR are reset
and the program beginning with the address indicated by the reset vector is executed. After reset, the
low-speed on-chip oscillator clock divided by 8 is automatically selected as the CPU clock.
The voltage monitor 2 does not reset some SFRs. Refer to 4. Special Function Registers (SFRs) for
details.
The internal RAM is not reset. When the input voltage to the VCC pin reaches the Vdet2 level or below
while writing to the internal RAM is in progress, the contents of internal RAM are undefined.
Refer to 7. Voltage Detection Circuit for details of voltage monitor 2 reset.
5.5
Watchdog Timer Reset
When the PM12 bit in the PM1 register is set to 1 (reset when watchdog timer underflows), the MCU
resets its pins, CPU, and SFR if the watchdog timer underflows. Then the program beginning with the
address indicated by the reset vector is executed. After reset, the low-speed on-chip oscillator clock
divided by 8 is automatically selected as the CPU clock.
The watchdog timer reset does not reset some SFRs. Refer to 4. Special Function Registers (SFRs)
for details.
The internal RAM is not reset. When the watchdog timer underflows, the contents of internal RAM are
undefined.
Refer to 13. Watchdog Timer for details of watchdog timer.
5.6
Software Reset
When the PM03 bit in the PM0 register is set to 1 (MCU reset), the MCU resets its pins, CPU, and SFR.
The program beginning with the address indicated by the reset vector is executed. After reset, the low-
speed on-chip oscillator clock divided by 8 is automatically selected for the CPU clock.
The software reset does not reset some SFRs. Refer to 4. Special Function Registers (SFRs) for
details.
The internal RAM is not reset.
Rev.1.30
Apr 14, 2006
REJ09B0222-0130
Page 27 of 233
5. Resets
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