Serial Flag Clear Trigger Register Mn (Sirmn) - Renesas RL78/G1P Hardware User Manual

RL78/G1P

11.3.6 Serial flag clear trigger register mn (SIRmn)

The SIRmn register is a trigger register that is used to clear each error flag of channel n.
When each bit (FECTmn, PECTmn, OVCTmn) of this register is set to 1, the corresponding bit (FEFmn, PEFmn,
OVFmn) of serial status register mn is cleared to 0. Because the SIRmn register is a trigger register, it is cleared
immediately when the corresponding bit of the SSRmn register is cleared.
The SIRmn register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the SIRmn register can be set with an 8-bit memory manipulation instruction with SIRmnL.
Reset signal generation clears the SIRmn register to 0000H.
Figure 11-8. Format of Serial Flag Clear Trigger Register mn (SIRmn)
Address: F0108H, F0109H (SIR00), F010AH, F010BH (SIR01)
Symbol 15 14
SIRmn 0 0
FEC
Tmn
0 Not cleared
1 Clears the FEFmn bit of the SSRmn register to 0.
PEC
Tmn
0 Not cleared
1 Clears the PEFmn bit of the SSRmn register to 0.
OVC
Tmn
0 Not cleared
1 Clears the OVFmn bit of the SSRmn register to 0.
Note The SIR01 register only.
Caution Be sure to clear bits 15 to 3 (or bits 15 to 2 for the SIR00 register) to "0".
Remarks 1. m: Unit number (m = 0), n: Channel number (n = 0, 1)
2. When the SIRmn register is read, 0000H is always read.
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
13 12 11 10
0 0 0 0
Clear trigger of framing error of channel n
Clear trigger of parity error flag of channel n
Clear trigger of overrun error flag of channel n
CHAPTER 11 SERIAL ARRAY UNIT
After reset: 0000H R/W
9 8 7 6
0 0 0 0
5 4 3 2
0 0 0 FECT PEC
Note
mn Tmn
1 0
OVC
Tmn
323