Power-On Reset Function - Renesas R8C/18 Series Hardware Manual

R8C/18 Group, R8C/19 Group
5.2

Power-On Reset Function

When the RESET pin is connected to the VCC pin via a pull-up resistor of about 5 kΩ, and the VCC pin
voltage level rises, the power-on reset function is enabled and the MCU resets its pins, CPU, and SFR.
When a capacitor is connected to the RESET pin, always keep the voltage to the RESET pin 0.8VCC or
more.
When the input voltage to the VCC pin reaches the Vdet1 level or above, the low-speed on-chip
oscillator clock starts counting. When the low-speed on-chip oscillator clock count reaches 32, the
internal reset signal is held "H" and the MCU enters the reset sequence (refer to Figure 5.3). The low-
speed on-chip oscillator clock divided by 8 is automatically selected as the CPU after reset.
Refer to 4. Special Function Registers (SFRs) for the status of the SFR after power-on reset.
The voltage monitor 1 reset is enabled after power-on reset.
Figure 5.6 shows an Example of Power-On Reset Circuit and Operation.
About
5 kΩ
V
det1
V
por1
Internal reset signal
(active "L")
NOTES:
1. The supply voltage must be held within the MCU's operating voltage range (Vccmin or above) over the sampling time.
2. A sampling clock can be selected. Refer to 7. Voltage Detection Circuit for details.
3. Vdet1 indicates voltage detection level for the voltage detection 1 circuit. Refer to 7. Voltage Detection Circuit for details.
4. Refer to 18. Electrical Characteristics.
Figure 5.6 Example of Power-On Reset Circuit and Operation
Rev.1.30 Apr 14, 2006
REJ09B0222-0130
VCC
RESET
(3)
t
t
w(Vpor1–Vdet1)
w(por1)
Page 26 of 233
0.1 V to 2.7 V
VCC
0 V
RESET
0 V
(1, 2)
Sampling time
1
× 32
f
RING-S
0.8 VCC or above
within td(P-R)
V
Vccmin
V
por2
t t
w(por2) w(Vpor2–Vdet1)
1
× 32
f
RING-S
5. Resets
(3)
det1