Calculating Transfer Clock Frequency - Renesas RL78/G1P Hardware User Manual

RL78/G1P

11.5.8 Calculating transfer clock frequency

The transfer clock frequency for 3-wire serial I/O (CSI00) communication can be calculated by the following
expressions.
(1) Master
(Transfer clock frequency) = {Operation clock (f
(2) Slave
(Transfer clock frequency) = {Frequency of serial clock (SCK) supplied by master}
Note The permissible maximum transfer clock frequency is f
Remark The value of SDRmn[15:9] is the value of bits 15 to 9 of serial data register mn (SDRmn) (0000000B to
1111111B) and therefore is 0 to 127.
The operation clock (f
MCK
register mn (SMRmn).
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
MCK
) is determined by serial clock select register m (SPSm) and bit 15 (CKSmn) of serial mode
CHAPTER 11 SERIAL ARRAY UNIT
) frequency of target channel} ÷ (SDRmn[15:9] + 1) ÷ 2 [Hz]
/6.
MCK
Note
[Hz]
396