Interrupt Response Time; Variation Of Ipl When Interrupt Request Is Accepted - Renesas M16C/64A Series User Manual

M16C/64A Group
14.7.3

Interrupt Response Time

Figure 14.4 shows the Interrupt Response Time. The interrupt response or interrupt acknowledge time
denotes the time from when an interrupt request is generated until the first instruction in the interrupt
routine is executed. Specifically, it consists of the time from when an interrupt request is generated until
the executing instruction is completed ((a) in Figure 14.4) and the time during which the interrupt
sequence is executed ((b) in Figure 14.4).
Interrupt request
generated
Instruction
(a) The time from when an interrupt request is generated until the instruction being executed is completed.
The length of this time varies with the instruction being executed. The DIVX instruction requires the
longest time, which is equal to 30 cycles (no wait state, and when the divisor is a register).
(b) The time during which the interrupt sequence is executed. For details, see the table below. Note,
however, that the values in this table must be increased by two cycles for the DBC interrupt and by one
cycle for the address match and single-step interrupts.
Interrupt Vector Address
Even
Even
Odd
Odd
Figure 14.4 Interrupt Response Time
14.7.4

Variation of IPL When Interrupt Request is Accepted

When a maskable interrupt request is accepted, the interrupt priority level of the accepted interrupt is
set in the IPL.
When a software interrupt or special interrupt request is accepted, one of the interrupt priority levels
listed in Table 14.10 is set in the IPL. Table 14.10 lists the IPL Level Set in IPL When Software or
Special Interrupt is Accepted.
Table 14.10 IPL Level Set in IPL When Software or Special Interrupt is Accepted
Watchdog timer, NMI , oscillator stop/restart detect,
voltage monitor 1, voltage monitor 2
Software, address match, DBC , single-step
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
Interrupt request
acknowledged
Interrupt sequence
(a) (b)
Interrupt response time
SP Value
Even
Odd
Even
Odd
Interrupt Source
Instruction in
interrupt routine
16-bit Bus, No Wait States
18 cycles
19 cycles
19 cycles
20 cycles
Time
8-bit Bus, No Wait States
20 cycles
20 cycles
20 cycles
20 cycles
Level Set in IPL
7
Not changed
Page 212 of 800
14. Interrupts