Central Processing Unit (Cpu) - Renesas R8C/18 Series Hardware Manual

R8C/18 Group, R8C/19 Group
2.

Central Processing Unit (CPU)

Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB
configure a register bank. There are two sets of register bank.
b31
R2
R3
NOTE:
1. These registers comprise a register bank. There are two register banks.
Figure 2.1 CPU Registers
Rev.1.30 Apr 14, 2006
REJ09B0222-0130
b15
R0H (high-order of R0)
R1H (high-order of R1) R1L (low-order of R1)
b19 b15
INTBH
The 4-high order bits of INTB are INTBH and
the 16-low bits of INTB are INTBL.
b19
b15
b15
b15
b8
IPL
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b8b7
b0
R0L (low-order of R0)
R2
R3
A0
A1
FB
b0
INTBL
b0
PC
b0
USP
ISP
SB
b0
FLG
b0
b7
U I O B S Z D C
2. Central Processing Unit (CPU)
(1)
Data registers
(1)
Address registers
(1)
Frame base register
Interrupt table register
Program counter
User stack pointer
Interrupt stack pointer
Static base register
Flag register
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved bit
Processor interrupt priority level
Reserved bit