Central Processing Unit (Cpu) - Renesas M16C/64A Series User Manual

M16C/64A Group
2.

Central Processing Unit (CPU)

Figure 2.1 shows the CPU registers. Seven registers (R0, R1, R2, R3, A0, A1, and FB) out of 13 compose a
register bank, and there are two register banks.
b31
R2
R3
Note:
1. These registers compose a register bank. There are two register banks.
Figure 2.1 CPU Registers
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
b15
R0H (upper bits of R0)
R1H (upper bits of R1)
b19
b15
INTBH
INTBH is the 4 upper bits of the INTB register and INTBL
is the 16 lower bits.
b19
b15
b15
b15 b8
IPL
b8 b7 b0
R0L (lower bits of R0)
R1L (lower bits of R1)
R2
R3
A0
A1
FB
b0
INTBL
b0
PC
b0
USP
ISP
SB
b0
FLG
b7 b0
U I O B S Z D C
2. Central Processing Unit (CPU)
(1)
Data registers
(1)
Address registers
(1)
Frame base registers
Interrupt table register
Program counter
User stack pointer
Interrupt stack pointer
Static base register
Flag register
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area
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