Processor Mode; Processor Modes - Renesas R8C/18 Series Hardware Manual

R8C/18 Group, R8C/19 Group
8.

Processor Mode

8.1

Processor Modes

Single-chip mode can be selected as the processor mode. Table 8.1 lists Features of Processor Mode.
Figure 8.1 shows the PM0 Register and Figure 8.2 shows the PM1 Register.
Table 8.1 Features of Processor Mode
Processor Mode
Single-chip mode
Processor Mode Register 0
b7 b6 b5 b4 b3 b2 b1 b0
0 0 0
NOTE:
1. Set the PRC1 bit in the PRCR register to 1 (w rite enable) before rew riting the PM0 register.
Figure 8.1 PM0 Register
Processor Mode Register 1
b7 b6 b5 b4 b3 b2 b1 b0
0 0
NOTES:
1. Set the PRC1 bit in the PRCR register to 1 (w rite enable) before rew riting the PM1 register.
2. The PM12 bit is set to 1 by a program (and remains unchanged even if 0 is w ritten to it).
When the CSPRO bit in the CSPR register is set to 1 (count source protect mode enabled), the PM12 bit is
automatically set to 1.
Figure 8.2 PM1 Register
Rev.1.30 Apr 14, 2006
REJ09B0222-0130
Accessible Areas
SFR, internal RAM, internal ROM All pins are I/O ports or peripheral function
(1)
Symbol Address
PM0 0004h
Bit Symbol Bit Name
— Reserved bits
(b2-b0)
Softw are reset bit
PM03
— Nothing is assigned. If necessary, set to 0.
(b7-b4) When read, the content is 0.
(1)
Symbol Address
PM1 0005h
Bit Symbol Bit Name
— Nothing is assigned. If necessary, set to 0.
(b0) When read, the content is undefined.
— Reserved bit
(b1)
WDT interrupt/reset sw itch bit
PM12
— Nothing is assigned. If necessary, set to 0.
(b6-b3) When read, the content is 0.
— Reserved bit
(b7)
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Pins Assignable as I/O Port Pins
I/O pins.
After Reset
00h
Function
Set to 0.
The MCU is reset w hen this bit is set to 1.
When read, the content is 0.
After Reset
00h
Function
Set to 0.
0 : Watchdog timer interrupt
(2)
1 : Watchdog timer reset
Set to 0.
8. Processor Mode
RW
RW
RW
—
RW
—
RW
RW
—
RW