Bus - Renesas R8C/18 Series Hardware Manual

R8C/18 Group, R8C/19 Group
9.

Bus

The bus cycles differ when accessing ROM/RAM, and when accessing SFR. Table 9.1 lists Bus Cycles by
Access Space of the R8C/18 Group and Table 9.2 lists Bus Cycles by Access Space of the R8C/19 Group.
ROM/RAM and SFR are connected to the CPU by an 8-bit bus. When accessing in word (16-bit) units,
these areas are accessed twice in 8-bit units. Table 9.3 lists Access Units and Bus Operations.
Table 9.1 Bus Cycles by Access Space of the R8C/18 Group
Access Area
SFR
ROM/RAM
Table 9.2 Bus Cycles by Access Space of the R8C/19 Group
Access Area
SFR/data flash
Program ROM/RAM
Table 9.3 Access Units and Bus Operations
Area
Even address
Byte access
Odd address
Byte access
Even address
Word access
Odd address
Word access
Rev.1.30 Apr 14, 2006
REJ09B0222-0130
Bus Cycle
2 cycles of CPU clock
1 cycle of CPU clock
Bus Cycle
2 cycles of CPU clock
1 cycle of CPU clock
SFR, data flash
CPU clock
Even
Address
Data
CPU clock
Odd
Address
Data
CPU clock
Address
Even
Data
Data
CPU clock
Address
Odd
Data Data
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CPU clock
Address
Data
Data
CPU clock
Address
Data
Data
CPU clock
Address
Even + 1
Data
Data
CPU clock
Odd + 1
Address
Data
Data
ROM (program ROM), RAM
Even
Data
Odd
Data
Even Even + 1
Data
Odd Odd + 1
Data
9. Bus
Data
Data