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M16C/64A Group
6.4.4
Voltage Monitor 0 Reset
This reset is triggered by the MCU's on-chip voltage detector 0. The voltage detector 0 monitors the
voltage applied to the VCC1 pin (Vdet0).
The MCU resets the pins, CPU, and SFRs when the voltage applied to the VCC1 pin drops to Vdet0 or
below.
Then, the fOCO-S count starts when the voltage applied to the VCC1 pin rises to Vdet0 or above. The
internal reset signal becomes high after 32 cycles of fOCO-S, and then the MCU executes the program
at the address indicated by the reset vector. fOCO-S divided by 8 is automatically selected as the CPU
clock after reset.
The CWR bit in the RSTFR register becomes 0 (cold start) after voltage monitor 0 reset. Refer to 4.
"Special Function Registers (SFRs)" for the remaining SFR states after reset.
The internal RAM is not reset. When the voltage applied to the VCC1 pin drops to Vdet0 or below while
writing data to the internal RAM, the internal RAM becomes undefined.
Refer to 7. "Voltage Detector" for details of the voltage monitor 0 reset.
6.4.5
Voltage Monitor 1 Reset
This reset is triggered by the MCU's on-chip voltage detector 1. Voltage detector 1 monitors the voltage
applied to the VCC1 pin (Vdet1).
When the VW1C6 bit in the VW1C register is 1 (voltage monitor 1 reset when Vdet1 passage is
detected), the MCU resets the pins, CPU, and SFRs when the voltage applied to the VCC1 pin drops to
Vdet1 or below. fOCO-S divided by 8 is automatically selected as the CPU clock after reset. After tps +
60 cycles of the CPU clock has elapsed, the MCU executes the program at the address indicated by
the reset vector.
The LVD1R bit in the RSTFR register becomes 1 (voltage monitor 1 reset detected) after voltage
monitor 1 reset. Some SFRs are not reset at voltage monitor 1 reset. Refer to 4. "Special Function
Registers (SFRs)" for details. The processor mode remains unchanged since bits PM01 and PM00 in
the PM0 register are not reset.
The internal RAM is not reset.
Refer to 7. "Voltage Detector" for details of the voltage monitor 1 reset.
6.4.6
Voltage Monitor 2 Reset
This reset is triggered by the MCU's on-chip voltage detector 2. Voltage detector 2 monitors the voltage
applied to the VCC1 pin (Vdet2).
When the VW2C6 bit in the VW2C register is 1 (voltage monitor 2 reset when Vdet2 passage is
detected), the MCU resets the pins, CPU, and SFRs when the voltage applied to the VCC1 pin drops to
Vdet2 or below. fOCO-S divided by 8 is automatically selected as the CPU clock after reset. After tps +
60 cycles of the CPU clock has elapsed, the MCU executes the program at the address indicated by
the reset vector.
The LVD2R bit in the RSTFR register becomes 1 (voltage monitor 2 reset detected) after voltage
monitor 2 reset. Some SFRs are not reset at voltage monitor 2 reset. Refer to 4. "Special Function
Registers (SFRs)" for details. The processor mode remains unchanged since bits PM01 and PM00 in
the PM0 register are not reset.
The internal RAM is not reset.
Refer to 7. "Voltage Detector" for details of the voltage monitor 2 reset.
R01UH0136EJ0210 Rev.2.10
Jul 31, 2012
6. Resets
Page 55 of 800
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