Renesas R7FA0E1053CFJ Manuals

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Renesas R7FA0E1053CFJ User Manual

Renesas R7FA0E1053CFJ User Manual (734 pages)

32-Bit MCU

Brand: Renesas | Category: Microcontrollers | Size: 7 MB

Table of Contents

Corporate Headquarters
2
Contact Information
2
General Precautions in the Handling of Microprocessing Unit and Microcontroller Unit Products
3
About this Document
4
Typographic Notation
5
Special Terms
5
Register Description
6
Proprietary Notice
8
Table of Contents
9
Features
25
Overview
26
Function Outline
26
Block Diagram
30
Part Numbering
30
Function Comparison
33
Pin Functions
34
Pin Assignments
36
Pin Lists
39
Cpu
40
Overview
40
Debug
40
Operating Frequency
40
Block Diagram
40
Bus Matrix
41
Implementation Options
41
SWD Interface
42
Debug Function
42
Debug Mode Definition
42
Debug Mode Effects
42
Low Power Mode
42
Trace Control (for the MTB)
43
Coresight (for MTB)
43
Programmers Model
44
Address Spaces
44
Cortex-M23 Peripheral Address Map
44
External Debug Address Map
44
Coresight ROM Table
45
DBGREG Module
45
OCDREG Module
47
Systick Timer
50
OCD Emulator Connection
50
ID Code
50
Dbgen
50
Restrictions on Connecting an OCD Emulator
50
References
52
Usage Notes
52
Operating Modes
53
Overview
53
Operating Modes Transitions
53
Operating Mode Transitions
53
Address Space
54
Resets
55
Overview
55
Register Descriptions
57
RESF : Reset Status Flag Register
57
PORSR : Power-On Reset Status Register
58
Operation
58
RES Pin Reset
58
Power-On Reset
58
Voltage Monitor Reset
59
Independent Watchdog Timer Reset
60
Software Reset
60
Option-Setting Memory
61
Overview
61
Register Descriptions
61
OFS0 : Option Function Select Register 0
61
OFS1 : Option Function Select Register 1
63
AWS : Access Window Setting Register
65
OSIS : Ocd/Serial Programmer ID Setting Register
66
Setting Option-Setting Memory
67
Allocation of Data in Option-Setting Memory
67
Setting Data for Programming Option-Setting Memory
67
Usage Notes
68
Data for Programming Reserved Areas and Reserved Bits in the Option-Setting Memory
68
Note on FSPR Bit
68
Low Voltage Detection (LVD)
69
Overview
69
Register Descriptions
70
LVD1CR : Voltage Monitor 1 Circuit Control Register
70
LVD1MKR : Voltage Monitor 1 Circuit Mask Register
71
LVD1SR : Voltage Monitor 1 Circuit Status Register
72
VCC Input Voltage Monitor
72
Monitoring V Det0
72
Monitoring V Det1
72
Reset from Voltage Monitor 0
72
Interrupt and Reset from Voltage Monitor 1
73
Event Link Controller (ELC) Output
74
Clock Generation Circuit
75
Overview
75
Register Descriptions
77
CMC : Clock Operation Mode Control Register
77
SOMRG : Sub-Clock Oscillator Margin Check Register
79
FOCOSCR : FOCO Clock Source Control Register
79
FMAINSCR : FMAIN Clock Source Control Register
80
FSUBSCR : FSUB Clock Source Control Register
80
ICLKSCR : ICLK Clock Source Control Register
81
MOSCCR : Main Clock Oscillator Control Register
81
SOSCCR : Sub-Clock Oscillator Control Register
82
LOCOCR : Low-Speed On-Chip Oscillator Control Register
83
HOCOCR : High-Speed On-Chip Oscillator Control Register
84
MOCOCR : Middle-Speed On-Chip Oscillator Control Register
84
OSTC : Oscillation Stabilization Time Counter Status Register
85
OSTS : Oscillation Stabilization Time Select Register
87
OSCSF : Oscillation Stabilization Flag Register
88
HOCODIV : High-Speed On-Chip Oscillator Frequency Select Register
88
MOCODIV : Middle-Speed On-Chip Oscillator Frequency Select Register
89
MOSCDIV : MOSC Clock Division Register
89
OSMC : Subsystem Clock Supply Mode Control Register
90
CKS0 : Clock out Control Register 0
90
LIOTRM : Low-Speed On-Chip Oscillator Trimming Register
91
MIOTRM : Middle-Speed On-Chip Oscillator Trimming Register
92
HIOTRM : High-Speed On-Chip Oscillator Trimming Register
93
Main Clock Oscillator
93
Connecting a Crystal Resonator
93
External Clock Input
94
Notes on External Clock Input
94
Sub-Clock Oscillator
94
Connecting a 32.768-Khz Crystal Resonator
94
Internal Clock
95
System Clock (ICLK)
95
RTC-Dedicated Clock (RTCCLK)
97
IWDT Clock (IWDTCLK)
97
Systick Timer-Dedicated Clock (SYSTICCLK)
97
External Pin Output Clock (CLKOUT)
97
Usage Notes
98
Register Access
98
Notes on Clock Generation Circuit
98
Notes on Resonator
98
Notes on Board Design
98
Notes on Resonator Connect Pin
99
Low Power Modes
100
Overview
100
Register Descriptions
102
SBYCR : Standby Control Register
102
MSTPCRA : Module Stop Control Register a
103
MSTPCRB : Module Stop Control Register B
104
MSTPCRC : Module Stop Control Register C
104
MSTPCRD : Module Stop Control Register D
105
FLMODE : Flash Operating Mode Control Register
106
FLMWRP : Flash Operating Mode Protect Register
106
PSMCR : Power Save Memory Control Register
107
SYOCDCR : System Control OCD Control Register
108
Reducing Power Consumption by Switching Clock Signals
108
Module-Stop Function
108
Function for Lower Operating Power Consumption
108
Setting Operating Power Control Mode
108
Operating Range
110
High-Speed Mode
110
Sleep Mode
112
Transitioning to Sleep Mode
112
Canceling Sleep Mode
112
Software Standby Mode
113
Transition to Software Standby Mode
113
Canceling Software Standby Mode
113
Example of Software Standby Mode Application
114
Snooze Mode
114
Transition to Snooze Mode
114
Canceling Snooze Mode
115
Low Power Modes
116
Returning from Snooze Mode to Software Standby Mode
116
Snooze Operation Example
116
Usage Notes
117
Register Access
117
I/O Port Pin States
118
Module-Stop State of DTC
118
Internal Interrupt Sources
118
Transitioning to Low Power Modes
118
Timing of WFI Instruction
119
Writing to the IWDT Registers by DTC in Sleep Mode or Snooze Mode
119
Oscillators in Snooze Mode
119
Using SAU0 in Snooze Mode
119
Using UART0 in Snooze Mode
119
Register Write Protection
120
Overview
120
Register Descriptions
120
PRCR : Protect Register
120
Interrupt Controller Unit (ICU)
121
Overview
121
Register Descriptions
122
Irqcri : IRQ Control Register I (I = 0 to 5)
122
NMISR : Non-Maskable Interrupt Status Register
123
NMIER : Non-Maskable Interrupt Enable Register
124
NMICLR : Non-Maskable Interrupt Status Clear Register
125
NMICR : NMI Pin Interrupt Control Register
126
DTCENST0 : DTC Enable Status Register 0
126
DTCENST1 : DTC Enable Status Register 1
127
DTCENSET0 : DTC Enable Set Register 0
128
DTCENSET1 : DTC Enable Set Register 1
129
DTCENCLR0 : DTC Enable Clear Register 0
130
DTCENCLR1 : DTC Enable Clear Register 1
131
INTFLAG0 : Interrupt Request Flag Monitor Register 0
131
INTFLAG1 : Interrupt Request Flag Monitor Register 1
132
SBYEDCR0 : Software Standby/Snooze End Control Register 0
133
SBYEDCR1 : Software Standby/Snooze End Control Register 1
134
Vector Table
135
Interrupt Vector Table
136
Event Number
138
Interrupt Operation
139
Detecting Interrupts
139
Interrupt Setting Procedure
140
Enabling Interrupt Requests
140
Disabling Interrupt Requests
140
Polling for Interrupts
140
Selecting Interrupt Request Destinations
140
External Pin Interrupts
141
Non-Maskable Interrupt Operation
141
Return from Low Power Modes
142
Return from Sleep Mode
142
Return from Software Standby Mode
142
Return from Snooze Mode
142
Using the WFI Instruction with Non-Maskable Interrupts
142
Reference
142
Buses
143
Overview
143
Description of Buses
144
Main Buses
144
Slave Interface
144
Parallel Operations
144
Restriction on Endianness
144
Restriction on Exclusive Access
144
Register Descriptions
145
Busmcntx : Master Bus Control Register X (X = SYS, DMA)
145
Busnerradd : Bus Error Address Register N (N = 3, 4)
145
Busnerrstat : BUS Error Status Register N (N = 3, 4)
146
Bus Error Monitoring Section
146
Error Type that Occurs by Bus
146
Operation When a Bus Error Occurs
146
Conditions for Issuing Illegal Address Access Errors
147
References
147
Flash Read Protection (FRP)
148
Overview
148
Memory Protection
148
Usage Notes
149
Notes on the Use of a Debugger
149
Compiler Settings
149
Protection of OFS1 Register
149
Data Transfer Controller (DTC)
150
Overview
150
Register Descriptions
151
MRA : DTC Mode Register a
151
MRB : DTC Mode Register B
152
SAR : DTC Transfer Source Register
153
DAR : DTC Transfer Destination Register
154
CRA : DTC Transfer Count Register a
154
CRB : DTC Transfer Count Register B
155
DTCCR : DTC Control Register
155
DTCVBR : DTC Vector Base Register
155
DTCST : DTC Module Start Register
156
DTCSTS : DTC Status Register
156
Activation Sources
157
Allocating Transfer Information and DTC Vector Table
157
Operation
159
Transfer Information Read Skip Function
161
Transfer Information Write-Back Skip Function
161
Normal Transfer Mode
162
Repeat Transfer Mode
163
Block Transfer Mode
164
Chain Transfer
165
Operation Timing
166
Execution Cycles of DTC
168
DTC Bus Mastership Release Timing
169
DTC Setting Procedure
169
Examples of DTC Usage
170
Normal Transfer
170
Chain Transfer
170
Chain Transfer When Counter = 0
171
Interrupt
173
Interrupt Sources
173
Event Link
173
Low Power Consumption Function
173
Usage Notes
174
Transfer Information Start Address
174
Event Link Controller (ELC)
175
Overview
175
Register Descriptions
176
ELCR : Event Link Controller Register
176
Elsegrn : Event Link Software Event Generation Register N (N = 0, 1)
176
Elsrn : Event Link Setting Register N (N = 23 to 28)
177
Operation
178
Relation between Interrupt Handling and Event Linking
178
Linking Events
178
Example of Procedure for Linking Events
179
Usage Notes
179
Setting ELSR Register
179
Linking an Event from the same Function of the Destination
179
Linking DTC Transfer End Signals as Events
179
Setting Clocks
179
Module-Stop Function Setting
179
ELC Delay Time
179
Link Availability in Sleep, Software Standby, and Snooze Mode
180
I/O Ports
181
Overview
181
Register Descriptions
182
Podrm : Pmn Output Data Register (M = 0 to 9, N = 00 to 15)
182
Pdrm : Pmn Direction Register (M = 0 to 9, N = 00 to 15)
183
Pidrm : Pmn State Register (M = 0 to 9, N = 00 to 15)
184
Porrm : Pmn Output Reset Register (M = 0 to 9, N = 00 to 15)
184
Posrm : Pmn Output Set Register (M = 0 to 9, N = 00 to 15)
185
Eorrm : Pmn Event Output Reset Register (M = 1 to 2, N = 00 to 15)
186
Eosrm : Pmn Event Output Set Register (M = 1 to 2, N = 00 to 15)
186
Pmnpfs_A : Port Mn Pin Function Select Register (M = 1 to 4, N = 00 to 15)
187
P0Npfs_A : Port 0N Pin Function Select Register (N = 08 to 15)
189
P9Npfs_A : Port 9N Pin Function Select Register (N = 13 to 14)
189
PWPR : Write-Protect Register
190
Operation
190
General I/O Ports
190
Port Function Select
191
Port Group Function for ELC
191
Handling of Unused Pins
192
Usage Notes
193
Procedure for Specifying the Pin Functions
193
Port Output Data Register (PODR) Summary
193
Notes on Register Settings and Port Pin State
193
Notes on Using Analog Functions
193
Notes on Using Alternate Functions
193
Notes on Communications with Devices Operating at a Different Voltage (1.8 V, 2.5 V, or 3 V) by Switching I/O Buffers
199
Restriction on P206 Usage
200
Peripheral Select Settings for each Product
200
Timer Array Unit (TAU)
204
Overview
204
Register Descriptions
211
Tcr0N : Timer Counter Register 0N (N = 0 to 7)
211
Tdr0N/Tdr01X/Tdr03X : Timer Data Register 0N (N = 0 to 7) (X = L, H)
213
TPS0 : Timer Clock Select Register 0
213
Tmr0N : Timer Mode Register 0N (N = 0, 2, 4, 5, 6, 7)
217
Tmr0N : Timer Mode Register 0N (N = 1, 3)
219
Tsr0N : Timer Status Register 0N (N = 0 to 7)
221
TE0 : Timer Channel Enable Status Register 0
222
TS0 : Timer Channel Start Register 0
222
TT0 : Timer Channel Stop Register 0
223
TIS0 : Timer Input Select Register 0
224
TIS1 : Timer Input Select Register 1
224
TOE0 : Timer Output Enable Register 0
225
TO0 : Timer Output Register 0
225
TOL0 : Timer Output Level Register 0
226
TOM0 :Timer Output Mode Register 0
226
ISC : Input Switch Control Register
227
TNFEN : TAU Noise Filter Enable Register
228
Registers Controlling Port Functions of Pins to be Used for Timer I/O
228
Basic Rules of Timer Array Unit
229
Basic Rules of Simultaneous Channel Operation Function
229
Basic Rules of 8-Bit Timer Operation Function (Channels 1 and 3 Only)
230
Operations of Counters
231
Count Clock (F TCLK )
231
Timing of the Start of Counting
233
Operations of Counters
233
Channel Output (To0N Pin) Control
238
To0N Pin Output Circuit Configuration
238
To0N Pin Output Setting
239
Cautions on Channel Output Operation
240
Collective Manipulation of To0.To[N] Bit
243
Timer Interrupts and To0N Outputs When Counting Is Started
243
Timer Input (Ti0N) Control
244
Ti0N Input Circuit Configuration
244
Noise Filter
245
Cautions on Channel Input Operation
245
Independent Channel Operation Function of Timer Array Unit
245
Operation as an Interval Timer or for Square Wave Output
245
Operation as an External Event Counter
249
Operation as a Frequency Divider (Channel 0 of Unit 0 Only)
252
Operation for Input Pulse Interval Measurement
255
Operation for Input Signal High- or Low-Level Width Measurement
258
Operation as a Delay Counter
262
Simultaneous Channel Operation Function of Timer Array Unit
265
Operation for the One-Shot Pulse Output Function
265
Operation for the PWM Function
271
Operation for the Multiple PWM Output Function
277
Usage Notes
284
Cautions When Using Timer Output
284
Point for Caution When a Timer Output Is to be Used as an Event Input for the ELC
284
Bit Interval Timer (TML32)
285
Overview
285
Register Descriptions
287
ITLCAP00 : Interval Timer Capture Register 00
287
ITLCTL0 : Interval Timer Control Register
288
ITLCSEL0 : Interval Timer Clock Select Register 0
289
ITLFDIV00 : Interval Timer Frequency Division Register 0
290
ITLFDIV01 : Interval Timer Frequency Division Register 1
291
ITLCC0 : Interval Timer Capture Control Register 0
292
ITLS0 : Interval Timer Status Register
292
ITLMKF0 : Interval Timer Match Detection Mask Register
294
Operation
294
Counter Mode Settings
294
Capture Mode Settings
296
Timer Operation
297
Capture Operation
297
Interrupt
298
Interval Timer Setting Procedures
300
Realtime Clock (RTC)
303
Overview
303
Register Descriptions
304
RTCC0 : Realtime Clock Control Register 0
304
RTCC1 : Realtime Clock Control Register 1
305
SEC : Second Count Register
306
MIN : Minute Count Register
307
HOUR : Hour Count Register
307
DAY : Day Count Register
308
WEEK : Day-Of-Week Count Register
309
MONTH : Month Count Register
310
YEAR : Year Count Register
310
SUBCUD : Time Error Correction Register
311
ALARMWM : Alarm Minute Register
312
ALARMWH : Alarm Hour Register
312
ALARMWW : Alarm Day-Of-Week Register
312
Operation
313
Starting the Realtime Clock Operation
313
Shifting to Sleep or Software Standby Mode after Starting Operation
314
Reading from and Writing to the Counters of the Realtime Clock
315
Setting Alarm by the Realtime Clock
317
Hz Output by the Realtime Clock
318
Example of Time Error Correction by the Realtime Clock
318
Independent Watchdog Timer (IWDT)
323
Overview
323
Register Descriptions
324
IWDTRR : IWDT Refresh Register
324
IWDTSR : IWDT Status Register
325
OFS0 : Option Function Select Register 0
326
Operation
328
Auto Start Mode
328
Refresh Operation
329
Status Flags
330
Reset Output
331
Interrupt Sources
331
Reading the Down-Counter Value
331
Usage Notes
331
Refresh Operations
331
Clock Division Ratio Setting
332
Serial Array Unit (SAU)
333
Overview
333
Simplified SPI
333
Uart
334
Simplified I 2 C
335
Configuration of Serial Array Unit
335
Register Descriptions
338
Spsm : Serial Clock Select Register M (M = 0, 1)
338
Smrmn : Serial Mode Register Mn (Mn = 00, 02, 10)
340
Smrmn : Serial Mode Register Mn (Mn = 01, 03, 11)
341
Scrm0 : Serial Communication Operation Setting Register M0 (M = 0, 1)
342
Scrm1 : Serial Communication Operation Setting Register M1 (M = 0, 1)
344
SCR02 : Serial Communication Operation Setting Register 02
346
SCR03 : Serial Communication Operation Setting Register 03
347
Sdrmn : Serial Data Register Mn (Mn = 00, 01, 02, 03, 10, 11)
348
Sirmn : Serial Flag Clear Trigger Register Mn (Mn = 00, 02, 10)
349
Sirmn : Serial Flag Clear Trigger Register Mn (Mn = 01, 03, 11)
350
Ssrmn : Serial Status Register Mn (Mn = 00, 02, 10)
350
Ssrmn : Serial Status Register Mn (Mn = 01, 03, 11)
352
SS0 : Serial Channel Start Register 0
353
SS1 : Serial Channel Start Register 1
354
ST0 : Serial Channel Stop Register 0
354
ST1 : Serial Channel Stop Register 1
355
SE0 : Serial Channel Enable Status Register 0
355
SE1 : Serial Channel Enable Status Register 1
356
SOE0 : Serial Output Enable Register 0
356
SOE1 : Serial Output Enable Register 1
357
SO0 : Serial Output Register 0
357
SO1 : Serial Output Register 1
358
SOL0 : Serial Output Level Register 0
358
SOL1 : Serial Output Level Register 1
359
SSC0 : Serial Standby Control Register 0
360
ISC : Input Switch Control Register
361
SNFEN : SAU Noise Filter Enable Register
361
ULBS : UART Loopback Select Register
362
Operation Stop Mode
363
Operation of Simplified SPI
364
Master Transmission
365
Operation Procedure
367
Master Reception
372
Register Setting
373
Master Transmission and Reception
381
Slave Transmission
388
Slave Reception
396
Slave Transmission and Reception
401
Snooze Mode Function
410
Calculating Transfer Clock Frequency
413
Procedure for Processing Errors that Occurred During Simplified SPI Communication
415
Operation of UART Communication
415
UART Transmission
416
Register Setting
417
Operation Procedure
419
UART Reception
423
Processing Flow
428
Snooze Mode Function
429
Calculating Baud Rate
435
Procedure for Processing Errors that Occurred During UART Communication
437
Operation of LIN Communication
438
LIN Transmission
438
LIN Reception
441
Operation of Simplified I C Communication
444
Address Field Transmission
445
Register Setting
446
Data Transmission
449
Data Reception
452
Stop Condition Generation
457
Calculating Transfer Rate
458
Procedure for Processing Errors that Occurred During Simplified I 2 C Communication
458
C Bus Interface (IICA)
460
Overview
460
Register Descriptions
463
IICA0 : IICA Shift Register 0
463
SVA0 : Slave Address Register 0
464
IICCTL00 : IICA Control Register 00
464
IICS0 : IICA Status Register 0
468
IICF0 : IICA Flag Register 0
471
IICCTL01 : IICA Control Register 01
473
IICWL0 : IICA Low-Level Width Setting Register 0
475
IICWH0 : IICA High-Level Width Setting Register 0
475
Registers to Control the Port Function Multiplexed with the I 2 C I/O Pins
476
I 2 C Bus Definitions and Control Methods
476
Pin Configuration
476
Setting Transfer Clock Using IICWL0 and IICWH0 Registers
476
Start Conditions
477
Address
478
Transfer Direction Specification
478
Acknowledge (ACK)
478
Stop Condition
479
Clock Stretching
480
Release from Clock Stretching
481
Timing of Generation of the Interrupt Request Signal (IICA0_TXRXI) and Control of Clock Stretching
482
Address Match Detection Method
483
Error Detection
483
Extension Code
483
Arbitration
484
Wakeup Function
485
Communication Reservation
486
Usage Notes
488
Communication Operations
489
Timing of I C Interrupt Request Signal (IICA0_TXRXI) Occurrence
496
Master Device Operation
497
Operation Without Communication
505
Operation When Arbitration Loss Occurs (no Communication after Arbitration Loss)
506
Timing Charts
511
Serial Interface UARTA (UARTA)
526
Overview
526
Register Descriptions
528
TXBA0 : Transmit Buffer Register 0
528
RXBA0 : Receive Buffer Register 0
528
ASIMA00 : Operation Mode Setting Register 00
529
ASIMA01 : Operation Mode Setting Register 01
530
BRGCA0 : Baud Rate Generator Control Register 0
531
ASISA0 : Status Register 0
531
ASCTA0 : Status Clear Trigger Register 0
533
UTA0CK : UARTA Clock Select Register 0
534
ULBS : UART Loopback Select Register
534
Operation
535
Operation Stop Mode
535
UART Mode
535
Communication Procedure
535
Continuous Transmission
539
Reception Error
543
Receive Data Noise Filter
544
Baud Rate Generator
544
Configuration of Baud Rate Generator
544
Baud Rate Calculation
545
Usage Notes
549
Port Setting for RXDA0 Pin
549
Point for Caution When Selecting the UARTA0 Operation Clock (F UTA0 )
549
Point for Caution When Selecting the UARTA0 Operation Clock (F )
549
Cyclic Redundancy Check (CRC)
550
Overview
550
Register Descriptions
550
CRCCR0 : CRC Control Register 0
550
CRCDIR/CRCDIR_BY : CRC Data Input Register
551
CRCDOR/CRCDOR_HA : CRC Data Output Register
551
Cyclic Redundancy Check (CRC)
552
Operation
552
Basic Operation
552
Usage Notes
553
Settings for the Module-Stop State
553
Note on Transmission
553
Bit A/D Converter (ADC12)
555
Overview
555
Registers to Control the A/D Converter
559
ADM0 : A/D Converter Mode Register 0
559
ADM1 : A/D Converter Mode Register 1
569
ADM2 : A/D Converter Mode Register 2
570
Adcr/Adcrn: 12-Bit or 10-Bit A/D Conversion Result Register N (N = 0 to 3)
572
Adcrh/Adcrnh : 8-Bit A/D Conversion Result Register N (N = 0 to 3)
573
ADS : Analog Input Channel Specification Register
573
ADUL : Conversion Result Comparison Upper Limit Setting Register
575
ADLL : Conversion Result Comparison Lower Limit Setting Register
575
ADTES : A/D Test Register
575
A/D Converter Operations
576
Input Voltage and Conversion Results
577
A/D Converter Operation Modes
578
Software Trigger No-Wait Mode (Select Mode, Sequential Conversion Mode)
578
Software Trigger No-Wait Mode (Select Mode, One-Shot Conversion Mode)
579
Software Trigger No-Wait Mode (Scan Mode, Sequential Conversion Mode)
580
Software Trigger No-Wait Mode (Scan Mode, One-Shot Conversion Mode)
581
Software Trigger Wait Mode (Select Mode, Sequential Conversion Mode)
582
Software Trigger Wait Mode (Select Mode, One-Shot Conversion Mode)
583
Software Trigger Wait Mode (Scan Mode, Sequential Conversion Mode)
584
Software Trigger Wait Mode (Scan Mode, One-Shot Conversion Mode)
585
Hardware Trigger No-Wait Mode (Select Mode, Sequential Conversion Mode)
586
Hardware Trigger No-Wait Mode (Select Mode, One-Shot Conversion Mode)
587
Hardware Trigger No-Wait Mode (Scan Mode, Sequential Conversion Mode)
588
Hardware Trigger No-Wait Mode (Scan Mode, One-Shot Conversion Mode)
589
Hardware Trigger Wait Mode (Select Mode, Sequential Conversion Mode)
590
Hardware Trigger Wait Mode (Select Mode, One-Shot Conversion Mode)
591
Hardware Trigger Wait Mode (Scan Mode, Sequential Conversion Mode)
592
Hardware Trigger Wait Mode (Scan Mode, One-Shot Conversion Mode)
593
A/D Converter Setup Procedure
594
Setting up Software Trigger No-Wait Mode
594
Setting up Software Trigger Wait Mode
596
Setting up Hardware Trigger No-Wait Mode
597
Setting up Hardware Trigger Wait Mode
599
Example of Using the ADC12 When Selecting the Temperature Sensor Output Voltage or Internal Reference Voltage, and Software Trigger No-Wait Mode and One-Shot Conversion Mode
600
Setting up Test Mode
600
Snooze Mode Function
602
A/D Conversion by Inputting a Hardware Trigger
602
If an Interrupt Is Generated after A/D Conversion Ends
602
If no Interrupt Is Generated after A/D Conversion Ends
603
Testing of the A/D Converter
605
How to Read A/D Converter Characteristics Table
606
Overall Error
606
Quantization Error
606
Zero-Scale Error
607
Integral Linearity Error
607
Differential Linearity Error
607
Usage Notes
609
Conflicting Operations
609
Noise Countermeasures
610
Conversion Results Just after A/D Conversion Start
611
Starting the A/D Converter
611
Temperature Sensor (TSN)
612
Overview
612
Using the Temperature Sensor
612
Preparation for Using the Temperature Sensor
612
Procedures for Using the Temperature Sensor
613
Sram
614
Overview
614
Register Descriptions
614
PARIOAD : SRAM Parity Error Operation after Detection Register
614
SRAMPRCR : SRAM Protection Register
614
Operation
615
Parity Calculation Function
615
SRAM Error Sources
617
Access Cycle
617
Low-Power Function
618
Usage Notes
618
Instruction Fetch from the SRAM Area
618
SRAM Store Buffer
618
Flash Memory
619
Overview
619
Memory Structure
620
Register Descriptions
621
DFLCTL : Data Flash Control Register
621
FENTRYR : Flash P/E Mode Entry Register
621
FPR : Protection Unlock Register
622
FPSR : Protection Unlock Status Register
623
FPMCR : Flash P/E Mode Control Register
623
FISR : Flash Initial Setting Register
624
FRESETR : Flash Reset Register
625
FASR : Flash Area Select Register
626
FCR : Flash Control Register
626
FEXCR : Flash Extra Area Control Register
627
FSARH : Flash Processing Start Address Register H
629
FSARL : Flash Processing Start Address Register L
630
FEARH : Flash Processing End Address Register H
630
FEARL : Flash Processing End Address Register L
630
FWBL0 : Flash Write Buffer Register L0
631
FWBH0 : Flash Write Buffer Register H0
631
FSTATR1 : Flash Status Register 1
632
FSTATR2 : Flash Status Register 2
632
FEAMH : Flash Error Address Monitor Register H
633
FEAML : Flash Error Address Monitor Register L
634
FSCMR : Flash Startup Setting Monitor Register
634
FAWSMR : Flash Access Window Start Address Monitor Register
634
FAWEMR : Flash Access Window End Address Monitor Register
635
Uidrn : Unique ID Registers N (N = 0 to 3)
635
Pnrn : Part Numbering Register N (N = 0 to 3)
635
MCUVER : MCU Version Register
636
Operating Modes Associated with the Flash Memory
636
ID Code Protection
637
Overview of Functions
638
Configuration Area Bit Map
639
Startup Area Select
640
Protection by Access Window
640
Programming Commands
641
Suspend Operation
641
Protection
641
Startup Program Protection
641
Area Protection
642
Self-Programming
643
Overview
643
Background Operation
644
Programming and Erasure
644
Sequencer Modes
644
Read Mode
645
Software Commands
645
Software Command Usage
646
Reading the Flash Memory
657
Reading the Code Flash Memory
657
Reading the Data Flash Memory
657
Usage Notes
658
Erase Suspended Area
658
Constraints on Additional Writes
658
Reset During Programming and Erasure
658
Non-Maskable Interrupt Disabled During Programming and Erasure
658
Location of Interrupt Vectors During Programming and Erasure
658
Programming and Erasure in Subosc-Speed Operating Mode
658
Abnormal Termination During Programming and Erasure
658
Actions Prohibited During Programming and Erasure
658
Flash-IF Clock (ICLK) During Program/Erase
659
True Random Number Generator (TRNG)
660
Overview
660
Register Descriptions
660
TRNGSDR : TRNG Seed Data Register
660
TRNGSCR0 : TRNG Seed Command Register 0
660
TRNGSCR1 : TRNG Seed Command Register 1
661
Operation
661
Overall Processing Flow
661
Usage Notes
661
Internal Voltage Regulator
662
Overview
662
Operation
662
Electrical Characteristics
663
Absolute Maximum Ratings
663
Tj/Ta Definition
664
Oscillators Characteristics
665
Main Clock Oscillator Characteristics
665
Sub-Clock Oscillator Characteristics
665
On-Chip Oscillators Characteristics
665
DC Characteristics
666
Pin Characteristics
666
Operating and Standby Current
671
Thermal Characteristics
675
AC Characteristics
676
Reset Timing
679
Wakeup Time
681
Peripheral Function Characteristics
684
Serial Array Unit (SAU)
684
UART Interface (UARTA)
706
I 2 C Bus Interface (IICA)
707
Analog Characteristics
708
A/D Converter Characteristics
708
Absolute Accuracy
712
Offset Error
712
Full-Scale Error
713
Temperature Sensor/Internal Reference Voltage Characteristics
713
POR Characteristics
713
LVD Characteristics
714
Power Supply Voltage Rising Slope Characteristics
716
RAM Data Retention Characteristics
716
Flash Memory Programming Characteristics
716
Serial Wire Debug (SWD)
717
Appendix 1. Port States in each Processing Mode
720
Appendix 2. Package Dimensions
723
Appendix 3. I/O Registers
728
Peripheral Base Addresses
728
Access Cycles
728
Appendix 4. Peripheral Variant
730
Revision History
731

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