Renesas RX24T R5F524TAADFN 10 Manuals

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Renesas RX24T R5F524TAADFN 10 User Manual

Renesas RX24T R5F524TAADFN 10 User Manual (1230 pages)

32-Bit MCU

Brand: Renesas | Category: Microcontrollers | Size: 14 MB

Table of Contents

General Precautions in the Handling of MPU/MCU Products
4
How to Use this Manual
5
Description of Registers
6
List of Abbreviations and Acronyms
7
Table of Contents
8
Features
35
Overview
36
Outline of Specifications
36
List of Products
41
Block Diagram
42
Pin Functions
43
Pin Assignments
46
Cpu
53
Features
53
Register Set of the CPU
54
General-Purpose Registers (R0 to R15)
55
Control Registers
55
Interrupt Stack Pointer (Isp)/User Stack Pointer (USP)
56
Exception Table Register (EXTB)
56
Interrupt Table Register (INTB)
56
Program Counter (PC)
56
Processor Status Word (PSW)
57
Backup PC (BPC)
58
Backup PSW (BPSW)
59
Fast Interrupt Vector Register (FINTV)
59
Floating-Point Status Word (FPSW)
60
Accumulator
62
Processor Mode
63
Supervisor Mode
63
User Mode
63
Privileged Instruction
63
Switching between Processor Modes
63
Data Types
64
Integer
64
Floating-Points
65
Bitwise Operations
65
Strings
66
Endian
67
Switching the Endian
67
Access to I/O Registers
70
Notes on Access to I/O Registers
70
Data Arrangement
71
Data Arrangement in Registers
71
Data Arrangement in Memory
71
Notes on the Allocation of Instruction Codes
71
Vector Table
72
Exception Vector Table
72
Interrupt Vector Table
73
Operation of Instructions
74
Restrictions on RMPA and String-Manipulation Instructions
74
Transfer Size and Data Prefetching
74
Access to I/O Registers
74
Number of Cycles
75
Instruction and Number of Cycle
75
Numbers of Cycles for Response to Interrupts
79
Section 13.3.1, Acceptance Timing and Saved PC Value
79
Operating Modes
80
Operating Mode Types and Selection
80
Register Descriptions
81
Mode Monitor Register (MDMONR)
81
System Control Register 1 (SYSCR1)
82
Details of Operating Modes
83
Single-Chip Mode
83
Boot Mode
83
Boot Mode (SCI)
83
Transitions of Operating Modes
84
Operating Mode Transitions Determined by the Mode-Setting Pins
84
Address Space
85
I/O Registers
87
I/O Register Addresses (Address Order)
89
Resets
112
Overview
112
Register Descriptions
114
Reset Status Register 0 (RSTSR0)
114
Reset Status Register 1 (RSTSR1)
115
Reset Status Register 2 (RSTSR2)
116
Software Reset Register (SWRR)
117
Operation
118
RES# Pin Reset
118
Power-On Reset and Voltage Monitoring 0 Reset
118
Voltage Monitoring 1 Reset and Voltage Monitoring 2 Reset
120
Independent Watchdog Timer Reset
121
Software Reset
121
Determination of Cold/Warm Start
122
Determination of Reset Generation Source
123
Option-Setting Memory
124
Overview
124
Register Descriptions
125
Option Function Select Register 0 (OFS0)
125
Option Function Select Register 1 (OFS1)
127
Endian Select Register (MDE)
128
Usage Note
128
Setting Example of Option-Setting Memory
128
Voltage Detection Circuit (Lvdab)
129
Overview
129
Register Descriptions
132
Voltage Monitoring 1 Circuit Control Register 1 (LVD1CR1)
132
Voltage Monitoring 1 Circuit Status Register (LVD1SR)
133
Voltage Monitoring 2 Circuit Control Register 1 (LVD2CR1)
134
Voltage Monitoring 2 Circuit Status Register (LVD2SR)
135
Voltage Monitoring Circuit Control Register (LVCMPCR)
136
Voltage Detection Level Select Register (LVDLVLR)
137
Voltage Monitoring 1 Circuit Control Register 0 (LVD1CR0)
138
Voltage Monitoring 2 Circuit Control Register 0 (LVD2CR0)
139
VCC Input Voltage Monitor
140
Monitoring Vdet0
140
Monitoring Vdet1
140
Monitoring Vdet2
140
Reset from Voltage Monitor 0
141
Interrupt and Reset from Voltage Monitoring 1
142
Interrupt and Reset from Voltage Monitoring 2
144
Clock Generation Circuit
146
Overview
146
Register Descriptions
149
System Clock Control Register (SCKCR)
149
System Clock Control Register 3 (SCKCR3)
151
PLL Control Register (PLLCR)
152
PLL Control Register 2 (PLLCR2)
153
Main Clock Oscillator Control Register (MOSCCR)
154
Low-Speed On-Chip Oscillator Control Register (LOCOCR)
155
IWDT-Dedicated On-Chip Oscillator Control Register (ILOCOCR)
156
Oscillation Stabilization Flag Register (OSCOVFSR)
157
Oscillation Stop Detection Control Register (OSTDCR)
158
Oscillation Stop Detection Status Register (OSTDSR)
159
Main Clock Oscillator Wait Control Register (MOSCWTCR)
160
Main Clock Oscillator Forced Oscillation Control Register (MOFCR)
161
Memory Wait Cycle Setting Register (MEMWAIT)
162
Main Clock Oscillator
165
Connecting a Crystal
165
External Clock Input
166
Notes on the External Clock Input
166
Oscillation Stop Detection Function
167
Oscillation Stop Detection and Operation after Detection
167
Oscillation Stop Detection Interrupts
168
PLL Circuit
169
Internal Clock
169
System Clock
169
Peripheral Module Clock
169
Flashif Clock
169
CAC Clock
169
IWDT-Dedicated Clock
169
Usage Notes
170
Notes on Clock Generation Circuit
170
Notes on Resonator
170
Notes on Board Design
170
Clock Frequency Accuracy Measurement Circuit (CAC)
171
Overview
171
Register Descriptions
172
CAC Control Register 0 (CACR0)
172
CAC Control Register 1 (CACR1)
173
CAC Control Register 2 (CACR2)
174
CAC Interrupt Request Enable Register (CAICR)
175
CAC Status Register (CASTR)
176
CAC Upper-Limit Value Setting Register (CAULVR)
177
CAC Lower-Limit Value Setting Register (CALLVR)
177
CAC Counter Buffer Register (CACNTBR)
177
Operation
178
Measuring Clock Frequency
178
Digital Filtering of Signals on the CACREF Pin
179
Interrupt Requests
179
Usage Notes
180
Module Stop Function Setting
180
Low Power Consumption
181
Overview
181
Register Descriptions
185
Standby Control Register (SBYCR)
185
Module Stop Control Register a (MSTPCRA)
186
Module Stop Control Register B (MSTPCRB)
188
Module Stop Control Register C (MSTPCRC)
189
Operating Power Control Register (OPCCR)
190
Reducing Power Consumption by Switching Clock Signals
193
Module Stop Function
193
Function for Lower Operating Power Consumption
193
Setting Operating Power Control Mode
193
Low Power Consumption Modes
195
Sleep Mode
195
Entry to Sleep Mode
195
Exit from Sleep Mode
196
Deep Sleep Mode
197
Entry to Deep Sleep Mode
197
Exit from Deep Sleep Mode
198
Software Standby Mode
199
Entry to Software Standby Mode
199
Exit from Software Standby Mode
200
Example of Software Standby Mode Application
201
Usage Notes
202
I/O Port States
202
Module Stop State of DTC
202
On-Chip Peripheral Module Interrupts
202
Write Access to MSTPCRA, MSTPCRB, and MSTPCRC
202
Timing of WAIT Instructions
202
Rewrite the Register by DTC in Sleep Mode
202
Register Write Protection Function
203
Register Descriptions
204
Protect Register (PRCR)
204
Exception Handling
205
Exception Events
205
Undefined Instruction Exception
206
Privileged Instruction Exception
206
Access Exceptions
206
Floating-Point Exception
206
Reset
206
Non-Maskable Interrupt
206
Interrupt
206
Unconditional Trap
206
Exception Handling Procedure
207
Acceptance of Exception Events
209
Acceptance Timing and Saved PC Value
209
Vector and Site for Saving the Values in the PC and PSW
210
Hardware Processing for Accepting and Returning from Exceptions
211
Hardware Pre-Processing
212
Undefined Instruction Exception
212
Privileged Instruction Exception
212
Access Exceptions
212
Floating-Point Exception
212
Reset
212
Non-Maskable Interrupt
213
Interrupt
213
Unconditional Trap
213
Return from Exception Handling Routine
214
Priority of Exception Events
214
Interrupt Controller (Icub)
215
Overview
215
Register Descriptions
217
Interrupt Request Register N (Irn) (N = Interrupt Vector Number)
217
Edge Detection
217
Level Detection
217
Interrupt Request Enable Register M (Ierm) (M = 02H to 1Fh)
218
Interrupt Source Priority Register N (Iprn) (N = Interrupt Vector Number)
219
Fast Interrupt Set Register (FIR)
220
Software Interrupt Activation Register (SWINTR)
221
DTC Activation Enable Register N (Dtcern) (N = Interrupt Vector Number)
222
IRQ Control Register I (Irqcri) (I = 0 to 7)
223
IRQ Pin Digital Filter Enable Register 0 (IRQFLTE0)
224
IRQ Pin Digital Filter Setting Register 0 (IRQFLTC0)
225
Non-Maskable Interrupt Status Register (NMISR)
226
Non-Maskable Interrupt Enable Register (NMIER)
228
Non-Maskable Interrupt Status Clear Register (NMICLR)
229
NMI Pin Interrupt Control Register (NMICR)
230
NMI Pin Digital Filter Enable Register (NMIFLTE)
230
NMI Pin Digital Filter Setting Register (NMIFLTC)
231
Vector Table
232
Interrupt Vector Table
232
Fast Interrupt Vector Table
238
Non-Maskable Interrupt Vector Table
238
Interrupt Operation
239
Detecting Interrupts
239
Operation of Status Flags for Edge-Detected Interrupts
239
Operation of Status Flags for Level-Detected Interrupts
241
Enabling and Disabling Interrupt Sources
242
Selecting Interrupt Request Destinations
242
DTC Activation
242
Determining Priority
243
Multiple Interrupts
243
Fast Interrupt
244
Digital Filter
244
External Pin Interrupts
244
Non-Maskable Interrupt Operation
246
Return from Power-Down States
247
Return from Sleep Mode or Deep Sleep Mode
247
Return from Software Standby Mode
247
Usage Note
248
Note on WAIT Instruction Used with Non-Maskable Interrupt
248
Buses
249
Overview
249
Description of Buses
251
CPU Buses
251
Memory Buses
251
Internal Main Buses
251
Internal Peripheral Buses
252
Write Buffer Function (Internal Peripheral Bus)
253
Parallel Operation
254
Restrictions
255
Restrictions in Relation to RMPA and String-Manipulation Instructions
255
Register Descriptions
256
Bus Error Status Clear Register (BERCLR)
256
Bus Error Monitoring Enable Register (BEREN)
256
Bus Error Status Register 1 (BERSR1)
257
Bus Error Status Register 2 (BERSR2)
257
Bus Priority Control Register (BUSPRI)
258
Bus Error Monitoring Section
260
Types of Bus Error
260
Illegal Address Access
260
Timeout
260
Operations When a Bus Error Occurs
261
Conditions Leading to Bus Errors
261
Interrupt
262
Interrupt Source
262
Memory-Protection Unit (MPU)
263
Overview
263
Types of Access Control
265
Regions for Access Control
265
Background Region
265
Overlap between Regions
265
Instructions and Data that Span Regions
265
Register Descriptions
266
Region-N Start Page Number Register (Rspagen) (N = 0 to 7)
266
Region-N End Page Number Register (Repagen) (N = 0 to 7)
267
Memory-Protection Enable Register (MPEN)
268
Background Access Control Register (MPBAC)
269
Memory-Protection Error Status-Clearing Register (MPECLR)
270
Memory-Protection Error Status Register (MPESTS)
271
Data Memory-Protection Error Address Register (MPDEA)
272
Region Search Address Register (MPSA)
273
Region Search Operation Register (MPOPS)
273
Region Invalidation Operation Register (MPOPI)
274
Instruction-Hit Region Register (MHITI)
275
Data-Hit Region Register (MHITD)
277
Functions
279
Memory Protection
279
Region Search
279
Protection of Registers Related to the Memory-Protection Unit
279
Flow for Determination of Access by the Memory-Protection Function
280
Procedures for Using Memory Protection
282
Setting Access-Control Information
282
Enabling Memory Protection
282
Transition to User Mode
282
Processing in Response to Memory-Protection Errors
282
Data Transfer Controller (Dtca)
284
Overview
284
Register Descriptions
286
DTC Mode Register a (MRA)
286
DTC Mode Register B (MRB)
287
DTC Transfer Source Register (SAR)
288
DTC Transfer Destination Register (DAR)
288
DTC Transfer Count Register a (CRA)
289
DTC Transfer Count Register B (CRB)
290
DTC Control Register (DTCCR)
290
DTC Vector Base Register (DTCVBR)
291
DTC Address Mode Register (DTCADMOD)
291
DTC Module Start Register (DTCST)
292
DTC Status Register (DTCSTS)
293
Activation Sources
294
Allocating Transfer Information and DTC Vector Table
294
Operation
296
Transfer Information Read Skip Function
298
Transfer Information Write-Back Skip Function
299
Normal Transfer Mode
300
Repeat Transfer Mode
301
Block Transfer Mode
302
Chain Transfer
303
Operation Timing
304
Execution Cycles of the DTC
307
DTC Bus Mastership Release Timing
307
DTC Setting Procedure
308
Examples of DTC Usage
309
Normal Transfer
309
Chain Transfer When the Counter = 0
310
Interrupt Source
311
Low Power Consumption Function
312
Deep Sleep Mode
312
Software Standby Mode
312
Usage Notes
313
Transfer Information Start Address
313
Allocating Transfer Information
313
I/O Ports
314
Overview
314
I/O Port Configuration
317
Register Descriptions
319
Port Direction Register (PDR)
319
Port Output Data Register (PODR)
320
Port Input Data Register (PIDR)
321
Port Mode Register (PMR)
322
Open Drain Control Register 0 (ODR0)
323
Open Drain Control Register 1 (ODR1)
324
Pull-Up Control Register (PCR)
325
Drive Capacity Control Register (DSCR)
326
Initialization of the Port Direction Register (PDR)
327
Handling of Unused Pins
328
Multi-Function Pin Controller (MPC)
329
Overview
329
Register Descriptions
335
Write-Protect Register (PWPR)
335
P0N Pin Function Control Register (P0Npfs) (N = 0 to 2)
336
P1N Pin Function Select Register (P1Npfs) (N = 0, 1)
337
P2N Pin Function Select Register (P2Npfs) (N = 0 to 4)
338
P3N Pin Function Select Register (P3Npfs) (N = 0 to 3)
339
P4N Pin Function Select Register (P4Npfs) (N = 0 to 7)
340
P5N Pin Function Select Register (P5Npfs) (N = 0 to 5)
340
P6N Pin Function Select Register (P6Npfs) (N = 0 to 5)
341
P7N Pin Function Select Register (P7Npfs) (N = 0 to 6)
342
P8N Pin Function Select Register (P8Npfs) (N = 0 to 2)
343
P9N Pin Function Select Register (P9Npfs) (N = 0 to 6)
344
Pan Pin Function Select Register (Panpfs) (N = 0 to 5)
345
Pbn Pin Function Select Register (Pbnpfs) (N = 0 to 7)
346
Pdn Pin Function Select Register (Pdnpfs) (N = 0 to 7)
347
Pen Pin Function Select Register (Penpfs) (N = 0 to 5)
349
Usage Notes
351
Procedure for Specifying Input/Output Pin Function
351
Notes on MPC Register Setting
351
Note on Using Analog Functions
352
Note on PB1/PB2 Pin Input Level
352
Multi-Function Timer Pulse Unit (Mtu3D)
353
Overview
353
Register Descriptions
359
Timer Control Register (TCR)
359
Timer Control Register 2 (TCR2)
361
Timer Mode Register 1 (TMDR1)
365
Timer Mode Registers 2 (TMDR2A, TMDR2B)
367
Timer Mode Register 3 (TMDR3)
368
Timer I/O Control Register (TIOR)
369
Timer Compare Match Clear Register (TCNTCMPCLR)
386
Timer Interrupt Enable Register (TIER)
387
Timer Status Register (TSR)
390
Timer Buffer Operation Transfer Mode Register (TBTM)
391
Timer Input Capture Control Register (TICCR)
392
Timer Synchronous Clear Register (TSYCR)
393
Timer Counter (TCNT)
394
Timer Longword Counter (TCNTLW)
394
Timer General Register (TGR)
395
Timer Longword General Registers (TGRALW, TGRBLW)
395
Timer Start Registers (TSTRA, TSTRB, TSTR)
396
Timer Synchronous Registers (TSYRA, TSYRB)
398
Timer Counter Synchronous Start Register (TCSYSTR)
400
Timer Read/Write Enable Registers (TRWERA, TRWERB)
402
Timer Output Master Enable Registers (TOERA, TOERB)
403
Timer Output Control Registers 1 (TOCR1A, TOCR1B)
405
Timer Output Control Registers 2 (TOCR2A, TOCR2B)
407
Timer Output Level Buffer Registers (TOLBRA, TOLBRB)
410
Timer Gate Control Registers (TGCRA, TGCRB)
411
Timer Subcounters (TCNTSA, TCNTSB)
412
Timer Cycle Data Registers (TCDRA, TCDRB)
412
Timer Cycle Buffer Registers (TCBRA, TCBRB)
413
Timer Dead Time Data Registers (TDDRA, TDDRB)
413
Timer Dead Time Enable Registers (TDERA, TDERB)
414
Timer Buffer Transfer Set Registers (TBTERA, TBTERB)
415
Timer Waveform Control Registers (TWCRA, TWCRB)
416
Noise Filter Control Register N (Nfcrn) (N = 0 to 4, 6, 7, 9, C)
418
Noise Filter Control Register 5 (NFCR5)
420
Timer A/D Converter Start Request Control Register (TADCR)
421
Timer A/D Converter Start Request Cycle Set Registers (TADCORA, TADCORB)
425
Timer A/D Converter Start Request Cycle Set Buffer Registers (TADCOBRA, TADCOBRB)
425
Timer Interrupt Skipping Mode Registers (TITMRA, TITMRB)
426
Timer Interrupt Skipping Set Registers 1 (TITCR1A, TITCR1B)
427
Timer Interrupt Skipping Counters 1 (TITCNT1A, TITCNT1B)
430
Timer Interrupt Skipping Set Registers 2 (TITCR2A, TITCR2B)
432
Timer Interrupt Skipping Counters 2 (TITCNT2A, TITCNT2B)
434
A/D Conversion Start Request Select Register 0 (TADSTRGR0)
435
A/D Conversion Start Request Select Register 1 (TADSTRGR1)
436
Bus Master Interface
437
Counter Operation
438
Basic Functions
438
Input Capture Function
442
Synchronous Operation
444
Buffer Operation
446
Cascaded Operation
450
PWM Modes
455
Phase Counting Mode
460
16-Bit Phase Counting Mode
460
Cascade Connection 32-Bit Phase Counting Mode
471
Reset-Synchronized PWM Mode
472
Complementary PWM Mode
475
PWM Mode
498
A/D Converter Start Request Delaying Function
517
Synchronous Operation of MTU0 to MTU4, MTU6, MTU7, and MTU9
523
External Pulse Width Measurement
526
Dead Time Compensation
527
TCNTU, TCNTV, and TCNTW Capture at Crest And/Or Trough in Complementary PWM Mode
529
Noise Filter Function
529
A/D Conversion Start Request Frame Synchronization Signal
530
Interrupt Sources
531
Interrupt Sources and Priorities
531
DTC Activation
533
A/D Converter Activation
534
Operation Timing
536
Input/Output Timing
536
Interrupt Signal Timing
542
Usage Notes
545
Module Stop Function Setting
545
Input Clock Restrictions
545
Note on Cycle Setting
545
Contention between TCNT Write and Clear Operations
546
Contention between TCNT Write and Increment Operations
546
Contention between TGR Write Operation and Compare Match
547
Contention between Buffer Register Write Operation and Compare Match
547
Contention between Buffer Register Write and TCNT Clear Operations
548
Contention between TGR Read Operation and Input Capture
548
Contention between TGR Write Operation and Input Capture
549
Contention between Buffer Register Write Operation and Input Capture
550
Contention between MTU2.TCNT Write Operation and Overflow/Underflow in Cascaded Operation
551
Counter Value When Count Operation Is Stopped in Complementary PWM Mode
552
Buffer Operation Setting in Complementary PWM Mode
552
Buffer Operation and Compare Match in Reset-Synchronized PWM Mode
553
Overflow in Reset-Synchronized PWM Mode
554
Contention between Overflow/Underflow and Counter Clearing
555
Contention between TCNT Write Operation and Overflow/Underflow
555
Note on Transition from Normal Mode or PWM Mode 1 to Reset-Synchronized PWM Mode
556
Output Level in Complementary PWM Mode and Reset-Synchronized PWM Mode
556
Simultaneous Input Capture in MTU1.TCNT and MTU2.TCNT in Cascade Connection
556
Interrupt Skipping Function 2
557
Notes When Complementary PWM Mode Output Protection Function Is Not Used
557
Notes Regarding Timer Counter (MTU5.TCNT) and Timer General Register (MTU5.TGR)
557
Notes to Prevent Malfunctions in Synchronous Clearing for Complementary PWM Mode
558
Continuous Output of Interrupt Signal in Response to a Compare Match
560
Usage Notes on A/D Converter Delaying Function in Complementary PWM Mode
560
MTU Output Pin Initialization
562
Operating Modes
562
Operation in Case of Re-Setting Due to Error During Operation
562
Overview of Initialization Procedures and Mode Transitions in Case of Error During Operation
563
Port Output Enable 3 (Poe3B)
589
Overview
589
Register Descriptions
592
Input Level Control/Status Register 1 (ICSR1)
592
Input Level Control/Status Register 2 (ICSR2)
593
Input Level Control/Status Register 3 (ICSR3)
594
Input Level Control/Status Register 4 (ICSR4)
595
Input Level Control/Status Register 5 (ICSR5)
596
Input Level Control/Status Register 6 (ICSR6)
597
Input Level Control/Status Register 7 (ICSR7)
598
Output Level Control/Status Register 1 (OCSR1)
599
Output Level Control/Status Register 2 (OCSR2)
600
Active Level Setting Register 1 (ALR1)
601
Active Level Setting Register 2 (ALR2)
603
Software Port Output Enable Register (SPOER)
605
Port Output Enable Control Register 1 (POECR1)
607
Port Output Enable Control Register 2 (POECR2)
608
Port Output Enable Control Register 4 (POECR4)
610
Port Output Enable Control Register 5 (POECR5)
613
Port Output Enable Control Register 7 (POECR7)
615
Port Output Enable Control Register 8 (POECR8)
617
Port Output Enable Comparator Detection Flag Register (POECMPFR)
619
Port Output Enable Comparator Request Select Register (POECMPSEL)
620
Operation
621
Input-Level Detection Operation
634
Output-Level Compare Operation
635
High-Impedance Control Using Registers
636
High-Impedance Control through Detection of Oscillation Stop
636
High-Impedance Control through Detection of the Comparator
636
Additional Functions for Controlling High-Impedance States
636
Release from High-Impedance State
636
POE Setting Procedure
638
Interrupts
638
Usage Notes
639
Transition to Low Power Consumption Mode
639
High-Impedance Control When the MTU Is Not Selected
639
When the POE Is Not Used
639
Bit Timer (TMR)
640
Overview
640
Register Descriptions
648
Timer Counter (TCNT)
648
Time Constant Register a (TCORA)
649
Time Constant Register B (TCORB)
649
Timer Control Register (TCR)
650
Timer Counter Control Register (TCCR)
651
Timer Control/Status Register (TCSR)
653
Operation
655
Pulse Output
655
External Counter Reset Input
656
Operation Timing
657
TCNT Count Timing
657
Timing of Interrupt Signal Output on a Compare Match
658
Timing of Timer Output Signal at Compare Match
658
Timing of Counter Clear by Compare Match
659
Timing of the External Reset for TCNT
659
Timing of Interrupt Signal Output on an Overflow
660
Operation with Cascaded Connection
661
16-Bit Count Mode
661
Compare Match Count Mode
661
Interrupt Sources
662
Interrupt Sources and DTC Activation
662
Startup of the A/D Converter
663
Usage Notes
664
Module Stop State Setting
664
Section 11, Low Power Consumption
664
Notes on Setting Cycle
664
Conflict between TCNT Write and Counter Clear
664
Conflict between TCNT Write and Increment
665
Conflict between TCORA or TCORB Write and Compare Match
665
Conflict between Compare Matches a and B
666
Switching of Internal Clocks and TCNT Operation
666
Clock Source Setting with Cascaded Connection
668
Continuous Output of Compare Match Interrupt Signal
668
Compare Match Timer (CMT)
669
Overview
669
Register Descriptions
670
Compare Match Timer Start Register 0 (CMSTR0)
670
Compare Match Timer Start Register 1 (CMSTR1)
670
Compare Match Timer Control Register (CMCR)
671
Compare Match Counter (CMCNT)
672
Compare Match Constant Register (CMCOR)
672
Operation
673
Periodic Count Operation
673
CMCNT Count Timing
673
Interrupts
674
Interrupt Sources
674
Timing of Compare Match Interrupt Generation
674
Usage Notes
675
Setting the Module Stop Function
675
Conflict between CMCNT Counter Writing and Compare Match
675
Conflict between CMCNT Counter Writing and Incrementing
675
Independent Watchdog Timer (Iwdta)
676
Overview
676
Register Descriptions
678
IWDT Refresh Register (IWDTRR)
678
IWDT Control Register (IWDTCR)
679
IWDT Status Register (IWDTSR)
682
IWDT Reset Control Register (IWDTRCR)
683
IWDT Count Stop Control Register (IWDTCSTPR)
684
Option Function Select Register 0 (OFS0)
684
Operation
685
Count Operation in each Start Mode
685
Register Start Mode
685
Auto-Start Mode
687
Control over Writing to the IWDTCR, IWDTRCR, and IWDTCSTPR Registers
689
Refresh Operation
690
Status Flags
692
Reset Output
692
Interrupt Sources
692
Reading the Counter Value
693
Correspondence between Option Function Select Register 0 (OFS0) and IWDT Registers
694
Usage Notes
694
Refresh Operations
694
Clock Divide Ratio Setting
694
Serial Communications Interface (Scig)
695
Overview
695
Register Descriptions
700
Receive Shift Register (RSR)
700
Receive Data Register (RDR)
700
Receive Data Register H, L, HL (RDRH, RDRL, RDRHL)
701
Transmit Data Register (TDR)
701
Transmit Data Register H, L, HL (TDRH, TDRL, TDRHL)
702
Transmit Shift Register (TSR)
702
Serial Mode Register (SMR)
703
Serial Control Register (SCR)
707
Serial Status Register (SSR)
712
Smart Card Mode Register (SCMR)
717
Bit Rate Register (BRR)
719
Modulation Duty Register (MDDR)
727
Serial Extended Mode Register (SEMR)
728
Noise Filter Setting Register (SNFR)
731
I C Mode Register 1 (SIMR1)
732
I 2 C Mode Register 2 (SIMR2)
733
I 2 C Mode Register 3 (SIMR3)
734
I C Status Register (SISR)
736
SPI Mode Register (SPMR)
737
Operation in Asynchronous Mode
739
Serial Data Transfer Format
739
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
741
Clock
742
Double-Speed Mode
742
CTS and RTS Functions
743
SCI Initialization (Asynchronous Mode)
744
Serial Data Transmission (Asynchronous Mode)
745
Serial Data Reception (Asynchronous Mode)
749
Multi-Processor Communications Function
753
Multi-Processor Serial Data Transmission
754
Multi-Processor Serial Data Reception
755
Operation in Clock Synchronous Mode
758
Clock
758
CTS and RTS Functions
759
SCI Initialization (Clock Synchronous Mode)
760
Serial Data Transmission (Clock Synchronous Mode)
761
Serial Data Reception (Clock Synchronous Mode)
765
Simultaneous Serial Data Transmission and Reception (Clock Synchronous Mode)
768
Operation in Smart Card Interface Mode
769
Sample Connection
769
Data Format (Except in Block Transfer Mode)
770
Block Transfer Mode
771
Receive Data Sampling Timing and Reception Margin
772
SCI Initialization (Smart Card Interface Mode)
773
Serial Data Transmission (Except in Block Transfer Mode)
774
Serial Data Reception (Except in Block Transfer Mode)
777
Clock Output Control
779
Operation in Simple I C Mode
780
Generation of Start, Restart, and Stop Conditions
781
Clock Synchronization
783
SSDA Output Delay
784
SCI Initialization (Simple I 2 C Mode)
785
Operation in Master Transmission (Simple I 2 C Mode)
786
Master Reception (Simple I 2 C Mode)
788
Operation in Simple SPI Mode
790
States of Pins in Master and Slave Modes
791
SS Function in Master Mode
791
SS Function in Slave Mode
791
Relationship between Clock and Transmit/Receive Data
792
SCI Initialization (Simple SPI Mode)
793
Transmission and Reception of Serial Data (Simple SPI Mode)
793
Bit Rate Modulation Function
793
25.10 Noise Cancellation Function
794
25.11 Interrupt Sources
795
Buffer Operations for TXI and RXI Interrupts
795
Interrupts in Asynchronous Mode, Clock Synchronous Mode, and Simple SPI Mode
795
Interrupts in Smart Card Interface Mode
796
Interrupts in Simple I C Mode
797
25.12 Usage Notes
798
Setting the Module Stop Function
798
Break Detection and Processing
798
Mark State and Generating Breaks
798
Receive Error Flags and Transmit Operations (Clock Synchronous Mode and Simple SPI Mode)
798
Writing Data to the TDR Register
798
Restrictions on Clock Synchronous Transmission (Clock Synchronous Mode and Simple SPI Mode)
799
Continuous Transmission
799
Restrictions on Using DTC
800
Notes on Starting Transfer
800
SCI Operations During Low Power Consumption State
800
External Clock Input in Clock Synchronous Mode and Simple SPI Mode
803
Limitations on Simple SPI Mode
804
Slave Mode
804
Note on Transmit Enable Bit (te Bit)
805
I C-Bus Interface (Riica)
806
Overview
806
Register Descriptions
809
I 2 C-Bus Control Register 1 (ICCR1)
809
I 2 C-Bus Control Register 2 (ICCR2)
811
I 2 C-Bus Mode Register 1 (ICMR1)
815
I 2 C-Bus Mode Register 2 (ICMR2)
816
I 2 C-Bus Mode Register 3 (ICMR3)
818
I 2 C-Bus Function Enable Register (ICFER)
820
I 2 C-Bus Status Enable Register (ICSER)
822
I 2 C-Bus Interrupt Enable Register (ICIER)
824
I 2 C-Bus Status Register 1 (ICSR1)
826
I 2 C-Bus Status Register 2 (ICSR2)
829
Slave Address Register Ly (Sarly) (y = 0 to 2)
832
Slave Address Register Uy (Saruy) (y = 0 to 2)
833
I 2 C-Bus Bit Rate Low-Level Register (ICBRL)
834
I 2 C-Bus Bit Rate High-Level Register (ICBRH)
835
I 2 C-Bus Transmit Data Register (ICDRT)
837
I 2 C-Bus Receive Data Register (ICDRR)
837
I 2 C-Bus Shift Register (ICDRS)
837
Operation
838
Communication Data Format
838
Initial Settings
839
Master Transmit Operation
840
Master Receive Operation
843
Slave Transmit Operation
849
Slave Receive Operation
852
SCL Synchronization Circuit
854
SDA Output Delay Function
855
Digital Noise Filter Circuits
856
Address Match Detection
857
Slave-Address Match Detection
857
Detection of the General Call Address
859
Device-ID Address Detection
860
Host Address Detection
862
Automatic Low-Hold Function for SCL
863
Function to Prevent Wrong Transmission of Transmit Data
863
NACK Reception Transfer Suspension Function
864
Function to Prevent Failure to Receive Data
864
Arbitration-Lost Detection Functions
866
Master Arbitration-Lost Detection (MALE Bit)
866
Function to Detect Loss of Arbitration During NACK Transmission (NALE Bit)
868
Slave Arbitration-Lost Detection (SALE Bit)
869
26.10 Start Condition/Restart Condition/Stop Condition Issuing Function
870
Issuing a Start Condition
870
Issuing a Restart Condition
870
Issuing a Stop Condition
871
26.11 Bus Hanging
872
Timeout Function
872
Extra SCL Clock Cycle Output Function
874
RIIC Reset and Internal Reset
875
26.12 Smbus Operation
876
Smbus Timeout Measurement
876
Packet Error Code (PEC)
877
Smbus Host Notification Protocol (Notify ARP Master Command)
877
26.13 Interrupt Sources
878
Buffer Operation for TXI and RXI Interrupts
878
26.14 Resets and Register and Function States When Issuing each Condition
879
26.15 Usage Notes
880
Setting Module Stop Function
880
Notes on Starting Transfer
880
Serial Peripheral Interface (Rspib)
881
Overview
881
Register Descriptions
885
RSPI Control Register (SPCR)
885
RSPI Slave Select Polarity Register (SSLP)
887
RSPI Pin Control Register (SPPCR)
888
RSPI Status Register (SPSR)
889
RSPI Data Register (SPDR)
892
Bus Interface
893
RSPI Sequence Control Register (SPSCR)
895
RSPI Sequence Status Register (SPSSR)
896
RSPI Bit Rate Register (SPBR)
897
RSPI Data Control Register (SPDCR)
898
RSPI Clock Delay Register (SPCKD)
900
RSPI Slave Select Negation Delay Register (SSLND)
901
RSPI Next-Access Delay Register (SPND)
902
RSPI Control Register 2 (SPCR2)
903
RSPI Command Registers 0 to 7 (SPCMD0 to SPCMD7)
905
Operation
908
Overview of RSPI Operations
908
Controlling RSPI Pins
909
RSPI System Configuration Examples
910
Single Master/Single Slave (with this MCU Acting as Master)
910
Single Master/Single Slave (with this MCU Acting as Slave)
911
Single Master/Multi-Slave (with this MCU Acting as Master)
912
Single Master/Multi-Slave (with this MCU Acting as Slave)
913
Multi-Master/Multi-Slave (with this MCU Acting as Master)
914
Master (Clock Synchronous Operation)/Slave (Clock Synchronous Operation) (with this MCU Acting as Master)
915
Master (Clock Synchronous Operation)/Slave (Clock Synchronous Operation) (with this MCU Acting as Slave)
915
Data Format
916
When Parity Is Disabled (SPCR2.SPPE = 0)
917
When Parity Is Enabled (SPCR2.SPPE = 1)
921
Transfer Format
925
Cpha = 0
925
Cpha = 1
926
Communications Operating Mode
927
Full-Duplex Synchronous Serial Communications (SPCR.TXMD = 0)
927
Transmit Operations Only (SPCR.TXMD = 1)
928
Transmit Buffer Empty/Receive Buffer Full Interrupts
929
Error Detection
931
Overrun Error
932
Parity Error
934
Mode Fault Error
935
Underrun Error
935
Initializing RSPI
936
Initialization by Clearing the SPE Bit
936
System Reset
936
SPI Operation
937
Master Mode Operation
937
Sequence Control
938
Burst Transfer
940
Slave Mode Operation
947
Clock Synchronous Operation
951
Master Mode Operation
951
Slave Mode Operation
955
Loopback Mode
957
Self-Diagnosis of Parity Bit Function
958
Interrupt Sources
959
Usage Notes
960
Setting Module Stop Function
960
Note on Low Power Consumption Functions
960
Notes on Starting Transfer
960
Notes on the SPRF and SPTEF Flags
960
CRC Calculator (CRC)
961
Overview
961
Register Descriptions
962
CRC Control Register (CRCCR)
962
CRC Data Input Register (CRCDIR)
962
CRC Data Output Register (CRCDOR)
963
Operation
964
Usage Notes
967
Module Stop Function Setting
967
Note on Transmission
967
Overview
968
Register Descriptions
977
A/D Data Registers y (Addry)
977
A/D Data Duplication Register (ADDBLDR)
977
A/D Data Duplication Register a (ADDBLDRA)
977
A/D Data Duplication Register B (ADDBLDRB)
977
A/D Internal Reference Voltage Data Register (ADOCDR)
977
A/D Self-Diagnosis Data Register (ADRD)
979
A/D Control Register (ADCSR)
980
A/D Channel Select Register A0 (ADANSA0)
984
A/D Channel Select Register A1 (ADANSA1)
986
A/D Channel Select Register B0 (ADANSB0)
987
A/D Channel Select Register B1 (ADANSB1)
989
A/D Channel Select Register C0 (ADANSC0)
991
A/D Channel Select Register C1 (ADANSC1)
993
A/D-Converted Value Addition/Average Function Select Register 0 (ADADS0)
994
A/D-Converted Value Addition/Average Function Select Register 1 (ADADS1)
997
A/D-Converted Value Addition/Average Count Select Register (ADADC)
1000
A/D Control Extended Register (ADCER)
1001
A/D Conversion Start Trigger Select Register (ADSTRGR)
1003
A/D Conversion Extended Input Control Register (ADEXICR)
1006
A/D Group C Trigger Select Register (ADGCTRGR)
1007
A/D Sampling State Register N (Adsstrn) (N = 0 to 11, L, O)
1010
A/D Sample-And-Hold Circuit Control Register (ADSHCR)
1012
A/D Disconnection Detection Control Register (ADDISCR)
1013
A/D Group Scan Priority Control Register (ADGSPCR)
1014
A/D Programmable Gain Amplifier Control Register (ADPGACR)
1016
A/D Programmable Gain Amplifier Gain Setting Register 0 (ADPGAGS0)
1018
Operation
1020
Scanning Operation
1020
Single Scan Mode
1021
Basic Operation (Without Channel-Dedicated Sample-And-Hold Circuits)
1021
Basic Operation (with Channel-Dedicated Sample-And-Hold Circuits)
1022
Channel Selection and Self-Diagnosis (Without Channel-Dedicated Sample-And-Hold Circuits)
1023
Channel Selection and Self-Diagnosis (with Channel-Dedicated Sample-And-Hold Circuits)
1024
A/D Conversion of Internal Reference Voltage
1025
A/D Conversion in Double Trigger Mode
1026
A/D Conversion in Extended Double Trigger Mode
1027
Continuous Scan Mode
1029
Basic Operation (Without Channel-Dedicated Sample And-Hold Circuits)
1029
Basic Operation (with Channel-Dedicated Sample-And-Hold Circuits)
1030
Channel Selection and Self-Diagnosis (Without Channel-Dedicated Sample-And-Hold Circuits)
1031
Channel Selection and Self-Diagnosis (with Channel-Dedicated Sample-And-Hold Circuits)
1032
Group Scan Mode
1033
Basic Operation
1033
A/D Conversion in Double Trigger Mode
1034
Operation under Group Priority Control
1036
Analog Input Sampling Time and Scan Conversion Time
1054
Usage Example of A/D Data Register Automatic Clearing Function
1057
A/D-Converted Value Addition/Average Mode
1057
Disconnection Detection Assist Function
1057
Starting A/D Conversion with Asynchronous Trigger
1059
Starting A/D Conversion with Synchronous Trigger from Peripheral Module
1059
Programmable Gain Amplifier
1059
Interrupt Sources and DTC Transfer Requests
1060
Interrupt Requests
1060
Allowable Impedance of Signal Source
1060
Usage Notes
1061
Notes on Reading Data Registers
1061
Notes on Stopping A/D Conversion
1061
A/D Conversion Restarting Timing and Termination Timing
1062
Notes on Scan End Interrupt Handling
1062
Module Stop Function Setting
1062
Notes on Entering Low Power Consumption States
1062
Notes on Canceling Software Standby Mode
1062
Error in Absolute Accuracy When Disconnection Detection Assistance Is in Use
1062
Voltage Range of Analog Power Supply Pins
1063
Notes on Board Design
1063
Notes on Noise Prevention
1064
D/A Converter for Generating Comparator C Reference Voltage (DA)
1065
Overview
1065
Register Descriptions
1066
D/A Data Register 0 (DADR0)
1066
D/A Control Register (DACR)
1067
DADR0 Format Select Register (DADPR)
1067
Operation
1068
Usage Notes
1069
Module Stop Function Setting
1069
Operation of the D/A Converter in Module Stop State
1069
Operation of the D/A Converter in Software Standby Mode
1069
Setting the D/A Converter
1069
Comparator C (CMPC)
1070
Overview
1070
Register Descriptions
1073
Comparator Control Register (CMPCTL)
1073
Comparator Input Select Register (CMPSEL0)
1074
Comparator Reference Voltage Select Register (CMPSEL1)
1075
Comparator Output Monitor Register (CMPMON)
1076
Comparator External Output Enable Register (CMPIOC)
1076
Operation
1077
Comparator Operation Example
1077
Noise Filter
1078
Comparator Interrupts
1079
Comparator Pin Output
1079
Comparator Setting Flowchart
1080
Usage Notes
1082
Module Stop Function Setting
1082
Comparator C Operation in Module Stop State
1082
Comparator C Operation in Software Standby Mode
1082
Comparator Operation While the 12-Bit A/D Convertor Is in the Module-Stop State
1082
Setting the D/A Converter for Generating Comparator C Reference Voltage
1082
Data Operation Circuit (DOC)
1083
Overview
1083
Register Descriptions
1084
DOC Control Register (DOCR)
1084
DOC Data Input Register (DODIR)
1085
DOC Data Setting Register (DODSR)
1085
Operation
1086
Data Comparison Mode
1086
Data Addition Mode
1087
Data Subtraction Mode
1088
Interrupt Requests
1088
Usage Note
1088
Module Stop Function Setting
1088
Ram
1089
Overview
1089
Operation
1089
Low Power Consumption Function
1089
Flash Memory
1090
Overview
1090
ROM Area and Block Configuration
1091
E2 Dataflash Area and Block Configuration
1092
Register Descriptions
1093
E2 Dataflash Control Register (DFLCTL)
1093
Flash P/E Mode Entry Register (FENTRYR)
1094
Protection Unlock Register (FPR)
1095
Protection Unlock Status Register (FPSR)
1095
Flash P/E Mode Control Register (FPMCR)
1096
Flash Initial Setting Register (FISR)
1097
Flash Reset Register (FRESETR)
1099
Flash Area Select Register (FASR)
1099
Flash Control Register (FCR)
1100
Flash Extra Area Control Register (FEXCR)
1101
Flash Processing Start Address Register H (FSARH)
1103
Flash Processing Start Address Register L (FSARL)
1103
Flash Processing End Address Register H (FEARH)
1104
Flash Processing End Address Register L (FEARL)
1104
Flash Write Buffer N Register (Fwbn) (N = 0 to 3)
1104
Flash Status Register 0 (FSTATR0)
1106
Flash Status Register 1 (FSTATR1)
1108
Flash Error Address Monitor Register H (FEAMH)
1109
Flash Error Address Monitor Register L (FEAML)
1109
Flash Start-Up Setting Monitor Register (FSCMR)
1110
Flash Access Window Start Address Monitor Register (FAWSMR)
1110
Flash Access Window End Address Monitor Register (FAWEMR)
1111
Unique ID Register N (Uidrn) (N = 0 to 3)
1111
ROM Cache Enable Register (ROMCE)
1111
ROM Cache Invalidate Register (ROMCIV)
1112
Start-Up Program Protection
1113
Area Protection
1114
Programming and Erasure
1115
Sequencer Modes
1115
E2 Dataflash Access Disabled Mode
1115
Read Mode
1116
P/E Modes
1116
Mode Transitions
1116
Transition from E2 Dataflash Access Disable Mode to Read Mode
1116
Transition from Read Mode to P/E Mode
1117
Transition from P/E Mode to Read Mode
1119
Software Commands
1122
Software Command Usage
1123
Program
1123
Block Erase
1125
All-Block Erase
1127
Blank Check
1129
Start-Up Area Information Program/Access Window Information Program
1131
Forced Stop of Software Commands
1132
Interrupt
1132
Boot Mode
1133
Boot Mode (SCI)
1134
Operating Conditions in Boot Mode (SCI)
1134
Starting up in Boot Mode (SCI)
1135
Boot Mode (FINE Interface)
1136
Operating Conditions in Boot Mode (FINE Interface)
1136
Flash Memory Protection
1137
ID Code Protection
1137
Boot Mode ID Code Protection
1138
On-Chip Debugging Emulator ID Code Protection
1139
ROM Code Protection
1140
34.10 Communication Protocol
1141
State Transition in Boot Mode (SCI)
1141
Command and Response Configuration
1142
Response to Undefined Commands
1142
Boot Mode Status Inquiry
1143
Inquiry Commands
1144
Supported Device Inquiry
1144
Data Area Availability Inquiry
1145
User Area Information Inquiry
1145
Data Area Information Inquiry
1146
Block Information Inquiry
1146
Setting Commands
1147
Device Select
1147
Operating Frequency Select
1148
Program/Erase Host Command Wait State Transition
1149
ID Code Authentication Command
1150
ID Code Check
1150
Program/Erase Commands
1151
User/Data Area Program Preparation
1151
Program
1152
Data Area Program
1152
Erase Preparation
1154
Block Erase
1154
Read-Check Commands
1155
Memory Read
1155
User Area Checksum
1156
Data Area Checksum
1156
User Area Blank Check
1156
Data Area Blank Check
1157
Access Window Information Program
1158
Access Window Read
1159
Serial Programmer Operation in Boot Mode (SCI)
1160
Bit Rate Automatic Adjustment Procedure
1161
Procedure to Receive the MCU Information
1162
Procedure to Select the Device and Change the Bit Rate
1163
Transition to the Program/Erase Host Command Wait State
1164
Unlock Boot Mode ID Code Protection
1165
Erase the User Area and Data Area
1166
Program the User Area and Data Area
1167
Check Data in the User Area
1168
Check Data in the Data Area
1169
Set the Access Window in the User Area
1170
34.12 Rewriting by Self-Programming
1171
Overview
1171
34.13 Usage Notes
1172
34.14 Usage Notes in Boot Mode
1173
Electrical Characteristics
1174
Absolute Maximum Ratings
1174
DC Characteristics
1175
Normal I/O Pin Output Characteristics (1)
1183
Standard I/O Pin Output Characteristics (2)
1185
Standard I/O Pin Output Characteristics (3)
1187
RIIC Pin Output Characteristics
1189
AC Characteristics
1191
Clock Timing
1191
Reset Timing
1194
Timing of Recovery from Low Power Consumption Modes
1195
Control Signal Timing
1197
Timing of On-Chip Peripheral Modules
1198
A/D Conversion Characteristics
1208
Programmable Gain Amplifier Characteristics
1212
Comparator Characteristics
1213
D/A Conversion Characteristics
1214
Power-On Reset Circuit and Voltage Detection Circuit Characteristics
1215
Oscillation Stop Detection Timing
1218
35.10 ROM (Flash Memory for Code Storage) Characteristics
1219
35.11 E2 Dataflash Characteristics
1221
35.12 Usage Notes
1222
Connecting VCL Capacitor and Bypass Capacitors
1222
Appendix 1. Port States in each Processing Mode
1224
Appendix 2. Package Dimensions
1225
Revision History
1227
Back Cover
1230

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