Conversion Result Comparison Upper Limit Setting Register (Adul); Conversion Result Comparison Lower Limit Setting Register (Adll) - Renesas RL78/G1P Hardware User Manual

RL78/G1P

9.3.8 Conversion result comparison upper limit setting register (ADUL)

This register is used to specify the setting for checking the upper limit of the A/D conversion results.
The A/D conversion results and ADUL register value are compared, and interrupt signal (INTAD) generation is
controlled in the range specified for the ADRCK bit of A/D converter mode register 2 (ADM2) (shown in Figure 9-8).
The ADUL register can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to FFH.
Cautions 1. When 12-bit resolution A/D conversion is selected, the higher eight bits of the 12-bit A/D
conversion result register (ADCR) are compared with the ADUL and ADLL registers.
2. Only write new values to the ADUL and ADLL registers while conversion is stopped (ADCS = 0,
ADCE = 0).
3. The setting of the ADUL and ADLL registers must be greater than that of the ADLL register.
Figure 9-12. Format of Conversion Result Comparison Upper Limit Setting Register (ADUL)
Address: F0011H After reset: FFH R/W
Symbol 7
ADUL ADUL7

9.3.9 Conversion result comparison lower limit setting register (ADLL)

This register is used to specify the setting for checking the lower limit of the A/D conversion results.
The A/D conversion results and ADLL register value are compared, and interrupt signal (INTAD) generation is
controlled in the range specified for the ADRCK bit of A/D converter mode register 2 (ADM2) (shown in Figure 9-8).
The ADLL register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Figure 9-13. Format of Conversion Result Comparison Lower Limit Setting Register (ADLL)
Address: F0012H After reset: 00H R/W
Symbol 7
ADLL ADLL7
Cautions 1. When 12-bit resolution A/D conversion is selected, the higher eight bits of the 12-bit A/D
conversion result register (ADCR) are compared with the ADUL and ADLL registers.
2. Only write new values to the ADUL and ADLL registers while conversion is stopped (ADCS = 0,
ADCE = 0).
3. The setting of the ADUL and ADLL registers must be greater than that of the ADLL register.
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
6 5
ADUL6 ADUL5
6 5
ADLL6 ADLL5
4 3
ADUL4 ADUL3
4 3
ADLL4 ADLL3
CHAPTER 9 A/D CONVERTER
2 1
ADUL2 ADUL1
2 1
ADLL2 ADLL1
0
ADUL0
0
ADLL0
265