Timer Output Level Register M (Tolm) - Renesas RL78/G1P Hardware User Manual

RL78/G1P

6.3.11 Timer output level register m (TOLm)

The TOLm register is a register that controls the timer output level of each channel.
The setting of the inverted output of channel n by this register is reflected at the timing of set or reset of the timer output
signal while the timer output is enabled (TOEmn = 1) in the Slave channel output mode (TOMmn = 1). In the master
channel output mode (TOMmn = 0), this register setting is invalid.
The TOLm register can be set by a 16-bit memory manipulation instruction.
The lower 8 bits of the TOLm register can be set with an 8-bit memory manipulation instruction with TOLmL.
Reset signal generation clears this register to 0000H.
Address: F01BCH, F01BDH (TOL0)
Symbol 15 14
TOLm 0 0
TOL
mn
0 Positive logic output (active-high)
1 Negative logic output (active-low)
Caution Be sure to clear bits 15 to 4, and 0 to "0".
If the value of this register is rewritten during timer operation, the timer output logic is inverted when
Remarks 1.
the timer output signal changes next, instead of immediately after the register value is rewritten.
2. m: Unit number (m = 0), n: Channel number (n = 0 to 3)
R01UH0895EJ0100 Rev.1.00
Nov 29, 2019
Figure 6-19. Format of Timer Output Level register m (TOLm)
After reset: 0000H
13 12 11 10
0 0 0 0
Control of timer output level of channel n
R/W
9 8 7 6
0 0 0 0
CHAPTER 6 TIMER ARRAY UNIT
5 4 3 2
0 0 TOL TOL TOL
m3 m2
1 0
0
m1
154