Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1303

Universal Counter Configuration Mode Register
The register controls the operation of the universal counter, including counter enable and counter
CAN_UCCNF
mode selection.
UCE (R/W)
Universal Counter Enable
UCCT (R/W)
Universal Counter CAN Trigger
Figure 25-62: CAN_UCCNF Register Diagram
Table 25-57: CAN_UCCNF Register Fields
Bit No.
(Access)
7 UCE
(R/W)
6 UCCT
(R/W)
5 UCRC
(R/W)
3:0 UCCNF
(R/W)
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
15 14 13 12 11 10 9 8
0 0 0 0 0 0 0 0
Bit Name
Universal Counter Enable.
The CAN_UCCNF.UCE bit enables universal counter operation in the mode selected
by the CAN_UCCNF.UCCNF bits.
Universal Counter CAN Trigger.
The CAN_UCCNF.UCCT bit enables the universal counter trigger, directing the CAN
to re-load the counter on mailbox 4 reception in watchdog mode and clear the counter
on mailbox 4 reception in time stamp mode. This bit has no effect in all other modes.
Universal Counter Reload/Clear.
The CAN_UCCNF.UCRC bit re-loads or clears the universal counter, depending on
the counter mode. In watchdog mode, setting this bit directs the CAN to re-load the
counter. In all other modes, setting this bit directs the CAN to clear the counter.
Universal Counter Configuration.
The CAN_UCCNF.UCCNF bits select the universal counter operating mode. For more
information about these modes, see the Operating Modes section.
7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0
Description/Enumeration
0 Disable Counter
1 Enable Counter
0 Disable Trigger
1 Enable Trigger
0 No Action
1 Re-load or Clear the Counter
0 Reserved
1 Time Stamp Mode
2 Watchdog Mode
ADSP-SC58x CAN Register Descriptions
UCCNF (R/W)
Universal Counter Configuration
UCRC (R/W)
Universal Counter Reload/Clear
25–87