Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1312

MSI Architectural Concepts
• Internal Direct Memory Access Controller (IDMAC). This unit is responsible for exchanging data between the
FIFO and the host memory. A set of IDMAC registers is accessible to the host for controlling the IDMAC
operation.
• Card Interface Unit (CIU). This unit controls the card-specific protocols. Within the CIU, the command path
control unit and datapath control unit interface the controller to the command and data ports of the
SD/MMC/SDIO cards. The CIU also provides clock control.
Bus Interface Unit (BIU)
The BIU provides the following functions:
• Host interface
• Interrupt control
• Register access
• FIFO access
• Power and pull-up control and card detection
Host Interface Unit (HIU)
The Host Interface Unit (HIU) is a slave bus interface, which provides the interface between the MSI and the pro-
cessor system bus. It supports the burst accesses to the data FIFO address region only. The register address region is
accessed through the standard accesses.
Interrupt Controller Unit
The interrupt controller unit generates an interrupt that depends on the controller interrupt status, the interrupt-
mask register, and the global interrupt-enable register bit. Once an interrupt condition is detected, the software sets
the corresponding interrupt bit in the interrupt status register. The interrupt status bit remains set until the software
clears it by writing a 1 to the interrupt bit (a 0 leaves the bit unchanged).
NOTE: Before enabling the interrupt, programs must write 32'hFFFF_FFFF to the interrupt status register
(MSI_ISTAT) in order to clear any pending unserviced interrupts. When clearing interrupts during nor-
mal operation, only clear the interrupt bits that are serviced.
Register Unit
The register unit is part of the Bus Interface Unit (BIU). It provides read and write access to the registers.
All registers reside in the BIU clock domain. When a command is sent to a card by setting the
MSI_CMD.STARTCMD bit, all relevant registers needed for the CIU operation are transferred to the CIU block.
(The MSI_CMD.STARTCMD bit is bit[31] of the
the registers that are transferred from the BIU to the CIU. The software must wait for the hardware to clear the start
bit before writing to these registers again. The register unit has a hardware locking feature to prevent illegal writes to
registers.
Once a command start is issued by setting the MSI_CMD.STARTCMD bit, the following registers cannot be reprog-
rammed until the Card Interface Unit (CIU) accepts the command:
26–6
register). During this time, software must not write to
MSI_CMD
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference