Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1313

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MSI_CMD – Command
•
MSI_CMDARG – Command Argument
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– Byte Count
MSI_BYTCNT
•
MSI_BLKSIZ – Block Size
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MSI_CLKDIV – Clock Divider
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MSI_CLKEN – Clock Enable
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– Timeout
MSI_TMOUT
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– Card Type
MSI_CTYPE
The hardware resets the MSI_CMD.STARTCMD bit once the CIU accepts the command. If a host writes to any of
these registers during this locked time, then the write is ignored and the hardware lock error bit is set in the
MSI_ISTAT (status) register. Additionally, if the interrupt is enabled and not masked for a hardware lock error,
then an interrupt is sent to the host.
Once a command is accepted, software can send another command to the CIU which has a one-deep command
queue under the following conditions:
• If the previous command was not a data transfer command, the new command is sent to the card once the
previous command completes.
• If the previous command is a data transfer command and if the MSI_CMD.WTPRIVDATA bit is set for the
new command, the new command is sent to the card only when the data transfer completes.
• If the MSI_CMD.WTPRIVDATA is 0, then the new command is sent to the card as soon as the previous com-
mand is sent. Typically, software uses this option only to stop or abort a previous data transfer or query the card
status in the middle of a data transfer.
FIFO Controller Unit
The FIFO controller interfaces the internal FIFO to the host or DMA interface and the card controller unit. The
FIFO depth is configured for 1024 bytes. A single shared FIFO is used for read and write operations because read
and write transfers to the cards do not occur simultaneously.
Figure 26-2: Combined Transmit and Receive FIFO
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
HOST CLOCK DOMAIN
COMBINED FIFO
CONTROLLER
HOST/DMA
INTERFACE
FIFO DEPTH
CARD CLOCK DOMAIN
CARD
INTERFACE
Bus Interface Unit (BIU)
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