Page 1 Concerto F28M36x Technical Reference Manual Literature Number: SPRUHE8E October 2012 – Revised November 2019...
Page 2: Table Of Contents
1.10.2 CSM Impact on Other On-Chip Resources ............1.10.3 Incorporating Code Security in User Applications ..............1.10.4 Do's and Don'ts to Protect Security Logic Contents SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 3 GPTM Raw Interrupt Status (GPTMRIS) Register, offset 0x01C ........2.6.7 GPTM Masked Interrupt Status (GPTMMIS) Register, offset 0x020 ..........2.6.8 GPTM Interrupt Clear (GPTMICR) Register, offset 0x024 SPRUHE8E – October 2012 – Revised November 2019 Contents Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 4 4.2.1 Introduction ..................4.2.2 GPIO Module Overview ..................4.2.3 Configuration Overview ................4.2.4 Digital General Purpose I/O Control ....................4.2.5 Input Qualification Contents SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 5 ....................C-Boot ROM Description ..................6.6.1 C-Boot ROM Memory Map ................6.6.2 C-Boot ROM RAM Initialization ..................6.6.3 C-Boot ROM RAM Usage SPRUHE8E – October 2012 – Revised November 2019 Contents Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 6 Trip-Zone Submodule Control and Status Registers ............... 7.4.7 Digital Compare Submodule Registers ................7.4.8 GPTRIP Input Select Registers ................7.4.9 Event-Trigger Submodule Registers Contents SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 7 ................... 10.3.3 SOC Principle of Operation ..............10.3.4 ONESHOT Single Conversion Support ..................10.3.5 ADC Conversion Priority ................10.3.6 Simultaneous Sampling Mode SPRUHE8E – October 2012 – Revised November 2019 Contents Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 8 11.8.15 Destination Transfer Step Size Register (DST_TRANSFER_STEP) — EALLOW Protected ..11.8.16 Source/Destination Wrap Size Register (SRC/DST_WRAP_SIZE) — EALLOW protected) ......11.8.17 Source/Destination Wrap Count Register (SCR/DST_WRAP_COUNT) Contents SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 9 14.2.4 I2C Module START and STOP Conditions 1050 ................... 14.2.5 Serial Data Formats 1050 ..................14.2.6 NACK Bit Generation 1052 ..................14.2.7 Clock Synchronization 1053 SPRUHE8E – October 2012 – Revised November 2019 Contents Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 10 1093 ..................15.5.2 Overrun in the Receiver 1093 ............. 15.5.3 Unexpected Receive Frame-Synchronization Pulse 1095 ................. 15.5.4 Overwrite in the Transmitter 1097 Contents SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 11 15.9.10 Enable/Disable the Transmit Frame-Synchronization Ignore Function 1141 ..............15.9.11 Set the Transmit Companding Mode 1142 ................15.9.12 Set the Transmit Data Delay 1143 SPRUHE8E – October 2012 – Revised November 2019 Contents Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 12 16.6.3 DMA Channel Control Word (DMACHCTL), offset 0x008 1209 ................... 16.7 µDMA Register Descriptions 1212 ..............16.7.1 DMA Status (DMASTAT), offset 0x000 1212 Contents SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 13 General-Purpose Mode 1252 ................17.8.1 General Purpose Bus Operation 1255 ..................... 17.9 C28x Access to EPI 1260 ................... 17.9.1 Real-Time Window (RTW) 1261 SPRUHE8E – October 2012 – Revised November 2019 Contents Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 14 18.1.1 Block Diagram 1317 ....................18.2 Functional Description 1317 ..................18.2.1 Operation as a Device 1318 ................... 18.2.2 Operation as a Host 1322 Contents SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 15 18.5.37 USB Receive Control and Status Endpoint n Low Register (USBRXCSRL[1]- ....................USBRXCSRL[15]) 1382 18.5.38 USB Receive Control and Status Endpoint n High Register (USBRXCSRH[1]- ..................... USBRXCSRH[15]) 1385 SPRUHE8E – October 2012 – Revised November 2019 Contents Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 16 ......19.6.15 Ethernet MAC Transmission Request (MACTR) Register, offset 0x038 1438 ........19.6.16 Ethernet MAC Timer Support (MACTS) Register, offset 0x03C 1438 Contents SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 17 1504 ............21.7.8 UART Control Register (UARTCTL), offset 0x030 1505 ....... 21.7.9 UART Interrupt FIFO Level Select (UARTIFLS) Register, offset 0x034 1507 SPRUHE8E – October 2012 – Revised November 2019 Contents Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 18 22.7.7 I2C Slave Interrupt Clear (I2CSICR), offset 0x818 1548 ..................M3 Controller Area Network (CAN) 1549 ......................... 23.1 Overview 1550 ....................... 23.1.1 Features 1550 ..................23.1.2 Functional Description 1550 Contents SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 19 23.15.1 CAN Control Register (CAN CTL) 1581 ..............23.15.2 Error and Status Register (CAN ES) 1583 ..............23.15.3 Error Counter Register (CAN ERRC) 1585 SPRUHE8E – October 2012 – Revised November 2019 Contents Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 20 24.7.7 Exception Entry and Return 1627 ......................24.8 Fault Handling 1629 ..................... 24.8.1 Fault Types 1629 ................24.8.2 Fault Escalation and Hard Faults 1630 Contents SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 21 1670 ......25.6.5 Application Interrupt and Reset Control (APINT) Register, offset 0xD0C 1671 ............25.6.6 System Control (SYSCTRL) Register, offset 0xD10 1673 SPRUHE8E – October 2012 – Revised November 2019 Contents Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 22 25.7.4 MPU Region Base Address (MPUBASE) Register, Offset 0xD9c-0xDB4 1688 ......25.7.5 MPU Region Attribute and Size (MPUATTR) Register, offset 0xDA0-DB8 1689 ........................Revision History 1691 Contents SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 23 1-45. Control Subsystem Peripheral Configuration 1 (CCNF1) Register ..........1-46. Control Subsystem Peripheral Configuration 2 (CCNF2) Register ..........1-47. Control Subsystem Peripheral Configuration 3 (CCNF3) Register SPRUHE8E – October 2012 – Revised November 2019 List of Figures Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 24 1-93. Missing Clock Reference Limit (MCLKLIMIT) Register ..................1-94. C28 USER_SWREG1 Register ..................1-95. C28_USER_SWREG2 Register ..............1-96. System PLL Multiplier (SYSPLLMULT) Register List of Figures SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 25 ....................1-141. Z2_CSMKEY3 Register ....................1-142. Z2_ECSLKEY0 Register ....................1-143. Z2_ECSLKEY1 Register ....................1-144. Z1_CSMCR Register ....................1-145. Z2_CSMCR Register SPRUHE8E – October 2012 – Revised November 2019 List of Figures Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 26 Timer Daisy Chain ..................... 2-3. Edge-Count Mode Example ................2-4. 16-Bit Input Edge-Time Mode Example ..................... 2-5. 16-Bit PWM Mode Example List of Figures SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 27 GPIO Interrupt Sense (GPIOIS) Register ..............4-7. GPIO Interrupt Both Edges (GPIOIBE) Register ................4-8. GPIO Interrupt Event (GPIOIEV) Register SPRUHE8E – October 2012 – Revised November 2019 List of Figures Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 28 4-55. GPIO Port B Qualification Control (GPBCTRL) Register ............4-56. GPIO Port C Qualification Control (GPCCTRL) Register ............4-57. GPIO Port C Qualification Control (GPDCTRL) Register List of Figures SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 29 Sx SHRAM Master Select Register (MSxMSEL) ............. 5-10. M3 Sx SHRAM Configuration Register 1 (MSxSRCR1) ............. 5-11. M3 Sx SHRAM Configuration Register 2 (MSxSRCR2) SPRUHE8E – October 2012 – Revised November 2019 List of Figures Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 30 5-58. C28x CPU Corrected Read Error Address Register (CCPUCREADDR) ......... 5-59. C28x DMA Corrected Read Error Address Register (CDMACREADDR) ..............5-60. C28x Uncorrectable Error Flag Register (CUEFLG) List of Figures SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 31 5-106. Data Low Test Register (FDATAL_TEST) ................. 5-107. ECC Test Address Register (FADDR_TEST) ..................5-108. ECC Test Register (FECC_TEST) .................. 5-109. ECC Control Register (FECC_CTRL) SPRUHE8E – October 2012 – Revised November 2019 List of Figures Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 32 6-16. Overview of CopyData Function ................6-17. Overview of SCI Bootloader Operation ..................6-18. Overview of SCI_Boot Function ................6-19. Overview of SCI_GetWordData Function List of Figures SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 33 7-25. Up, Single Edge Asymmetric Waveform With Independent Modulation on EPWMxA and ....................EPWMxB—Active Low ..... 7-26. Up-Count, Pulse Placement Asymmetric Waveform With Independent Modulation on EPWMxA SPRUHE8E – October 2012 – Revised November 2019 List of Figures Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 34 7-70. ZVS Full-H Bridge Waveforms ..............7-71. Peak Current Mode Control of a Buck Converter ................7-72. Peak Current Mode Control Waveforms for List of Figures SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 35 7-119. Digital Compare B Control Register (DCBCTL) ..............7-120. Digital Compare Filter Control Register (DCFCTL) ............7-121. Digital Compare Capture Control Register (DCCAPCTL) SPRUHE8E – October 2012 – Revised November 2019 List of Figures Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 36 8-27. PWM Waveform Details of APWM Mode Operation ..................... 9-1. Optical Encoder Disk ............9-2. QEP Encoder Output Signal for Forward/Reverse Movement ..................... 9-3. Index Pulse Example List of Figures SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 37 ........................ 10-4. 32-bit Write ........................ 10-5. 16-bit Read ........................ 10-6. 32-bit Read ........................ 10-7. 64-bit Read ....................... 10-8. ADC Trigger SPRUHE8E – October 2012 – Revised November 2019 List of Figures Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 38 10-54. Comparator ................10-55. Comparator Control (COMPCTL) Register ............... 10-56. Compare Output Status (COMPSTS) Register ..................10-57. DAC Value (DACVAL) Register List of Figures SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 39 12-16. SPI Baud Rate Register (SPIBRR) — Address 7044h 1004 ..........12-17. SPI Emulation Buffer Register (SPIRXEMU) — Address 7046h 1005 SPRUHE8E – October 2012 – Revised November 2019 List of Figures Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 40 14-7. I2C Module 7-Bit Addressing Format (FDF = 0, XA = 0 in I2CMDR) 1051 ........... 14-8. I2C Module 10-Bit Addressing Format (FDF = 0, XA = 1 in I2CMDR) 1051 List of Figures SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 41 15-25. Proper Positioning of Frame-Synchronization Pulses 1097 ......... 15-26. Data in the McBSP Transmitter Overwritten and Thus Not Transmitted 1097 SPRUHE8E – October 2012 – Revised November 2019 List of Figures Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 42 15-73. Sample Rate Generator 1 Register (SRGR1) 1169 ............... 15-74. Sample Rate Generator 2 Register (SRGR2) 1169 ................15-75. Multichannel Control 1 Register (MCR1) 1171 List of Figures SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 43 16-40. DMA PrimeCell Identification 3 (DMAPCellID3) Register 1226 ...................... 17-1. EPI Block Diagram 1229 ................... 17-2. SDRAM Non-Blocking Read Cycle 1234 SPRUHE8E – October 2012 – Revised November 2019 List of Figures Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 44 17-46. EPI Write FIFO Count (EPIWFIFOCNT) Register [offset 0x204] 1294 ..........17-47. EPI DMA Transmit Count (EPIDMATXCNT) Register [offset 0x208] 1295 List of Figures SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 45 18-27. USB Transmit Functional Address Endpoint n Registers (USBTXFUNCADDR[n]) 1364 ........18-28. USB Transmit Hub Address Endpoint n Registers (USBTXHUBADDR[n]) 1365 SPRUHE8E – October 2012 – Revised November 2019 List of Figures Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 46 19-2. Ethernet MAC Block Diagram 1419 ......................19-3. Ethernet Frame 1419 ......19-4. Ethernet MAC Raw Interrupt Status/Acknowledge (MACRIS/MACIACK) Register 1425 List of Figures SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 47 ......................20-22. SSIPC Register 1475 ....................20-23. SSIPeriphID4 Register 1476 ....................20-24. SSIPeriphID5 Register 1477 ....................20-25. SSIPeriphID6 Register 1478 SPRUHE8E – October 2012 – Revised November 2019 List of Figures Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 48 22-2. I2C Bus Configuration 1523 ..................22-3. START and STOP Conditions 1523 ............... 22-4. Complete Data Transfer with a 7-Bit Address 1524 List of Figures SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 49 23-21. Error Counter Register (CAN ERRC) [offset = 0x08] 1585 ..............23-22. Bit Timing Register (CAN BTR) [offset = 0x0C] 1585 SPRUHE8E – October 2012 – Revised November 2019 List of Figures Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 50 ................ 25-6. Interrupt 32-63 Set Enable 1 (EN1) Register 1649 ................ 25-7. Interrupt 64-95 Set Enable 2 (EN2) Register 1649 List of Figures SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 51 1688 ..............25-50. MPU Region Base Address (MPUBASE) Register 1688 ............. 25-51. MPU Region Attribute and Size (MPUATTR) Register 1690 SPRUHE8E – October 2012 – Revised November 2019 List of Figures Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 52 ............1-46. Device Configuration 7 (DC7) Register Field Descriptions ..... 1-47. General Purpose Input/Output Peripheral Present (PPGPIO) Register Field Descriptions List of Tables SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 53 1-95. C28 External Interrupt 2 Counter Register (XINT2CTR) Field Descriptions ........1-96. C28 External Interrupt 3 Counter Register (XINT3CTR) Field Descriptions SPRUHE8E – October 2012 – Revised November 2019 List of Tables Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 54 1-142. C28 XCLKOUT Divider Register (CXCLK) Field Descriptions ................1-143. Z1_CSMKEY0 Register Field Descriptions ................1-144. Z1_CSMKEY1 Register Field Descriptions ................1-145. Z1_CSMKEY2 Register Field Descriptions List of Tables SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 55 1-191. MIPCCOUNTERH Register Field Descriptions ................1-192. CTOMIPCCOM Register Field Descriptions ................. 1-193. CTOMIPCADDR Register Field Descriptions ............... 1-194. CTOMIPCDATAW Register Field Descriptions SPRUHE8E – October 2012 – Revised November 2019 List of Tables Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 56 ......3-17. Watchdog Peripheral Identification 3 (WDTPeriphID3) Register Field Descriptions ....... 3-18. Watchdog PrimeCell Identification 0 (WDTPCellID0) Register Field Descriptions List of Tables SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 57 ..................4-43. Default State of Peripheral Input ....................... 4-44. GPIOA MUX ....................... 4-45. GPIOB MUX ......................4-46. C28 GPIOC MUX SPRUHE8E – October 2012 – Revised November 2019 List of Tables Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 58 4-93. GPIO Port G Data (GPGDAT) Register Field Descriptions ............. 4-94. Analog I/O DAT (AIODAT) Register Field Descriptions ............4-95. GPIO Port A Set (GPASET) Register Field Descriptions List of Tables SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 59 ....5-24. MTOC_MSG_RAM Test and Initialization Register (MTOCRTESTINIT) Field Descriptions ..........5-25. Cx RAM INITDONE Register 1 (CxRINITDONE1) Field Descriptions SPRUHE8E – October 2012 – Revised November 2019 List of Tables Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 60 5-73. C28x Corrected Error Threshold Register (CCETRES) Field Descriptions ...... 5-74. C28x Corrected Error Threshold Exceeded Flag Register (CCEFLG) Field Descriptions List of Tables SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 61 ..........5-122. Flash Read Margin Control Register (FSPRD) Field Descriptions ........... 5-123. Flash Bank Access Control Register (FBAC) Field Descriptions SPRUHE8E – October 2012 – Revised November 2019 List of Tables Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 62 6-24. General Structure Of Source Program Data Stream In 16-Bit Mode ..............6-25. LSB/MSB Loading Sequence in 8-Bit Data Stream List of Tables SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 63 7-42. Counter-Compare A Mirror Register (CMPAM) Field Descriptions ............7-43. Counter-Compare B Register (CMPBM) Field Descriptions ............7-44. Counter-Compare B Register (CMPB) Field Descriptions SPRUHE8E – October 2012 – Revised November 2019 List of Tables Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 64 7-90. Event-Trigger Force Register (ETFRC) Field Descriptions ....7-91. Event-Trigger Counter Initialization Control Register (ETCNTINITCTL) Field Descriptions ........7-92. Event-Trigger Counter Initialization Register (ETCNTINIT) Field Descriptions List of Tables SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 65 10-8. ADC Interrupt Flag Register (ADCINTFLG) Field Descriptions ........10-9. ADC Interrupt Flag Clear Register (ADCINTFLGCLR) Field Descriptions ..........10-10. ADC Interrupt Overflow Register (ADCINTOVF) Field Descriptions SPRUHE8E – October 2012 – Revised November 2019 List of Tables Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 66 11-17. Destination Transfer Step Size Register (DST_TRANSFER_STEP) Field Descriptions ......11-18. Source/Destination Wrap Size Register (SRC/DST_WRAP_SIZE) Field Descriptions ....11-19. Source/Destination Wrap Count Register (SCR/DST_WRAP_COUNT) Field Descriptions List of Tables SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 67 1049 ..................14-2. Ways to Generate a NACK Bit 1052 ..............14-3. Descriptions of the Basic I2C Interrupt Requests 1054 SPRUHE8E – October 2012 – Revised November 2019 List of Tables Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 68 15-29. Register Bit Used to Enable/Disable the Receive Frame-Synchronization Ignore Function 1120 ............15-30. Register Bits Used to Set the Receive Companding Mode 1121 List of Tables SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 69 15-78. Transmit Control 1 Register (XCR1) Field Descriptions 1166 ..........15-79. Frame Length Formula for Transmit Control 1 Register (XCR1) 1166 SPRUHE8E – October 2012 – Revised November 2019 List of Tables Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 70 16-31. DMA Channel Priority Set (DMAPRIOSET) Register Field Descriptions 1218 ........16-32. DMA Channel Priority Clear (DMAPRIOCLR) Register Field Descriptions 1219 List of Tables SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 71 17-31. EPI FIFO Level Selects (EPIFIFOLVL) Register Field Descriptions 1293 ..........17-32. EPI Write FIFO Count (EPIWFIFOCNT) Register Field Descriptions 1294 SPRUHE8E – October 2012 – Revised November 2019 List of Tables Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 72 18-26. USB Connect Timing Register (USBCONTIM) Field Descriptions 1362 ........18-27. USB OTG VBUS Pulse Timing Register (USBVPLEN) Field Descriptions 1362 List of Tables SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 73 18-67. USB Device RESUME Raw Interrupt Status Register (USBDRRIS) Field Descriptions 1402 ....... 18-68. USB Device RESUME Raw Interrupt Status Register (USBDRRIS) Field Descriptions 1403 SPRUHE8E – October 2012 – Revised November 2019 List of Tables Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 74 20-9. SSIIM Register Field Descriptions 1466 ................... 20-10. SSIRIS Register Field Descriptions 1467 .................. 20-11. SSIMIS Register Field Descriptions 1469 List of Tables SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 75 21-31. UART PrimeCell Identification 3 (UARTPCellID3) Register Field Descriptions 1520 ............22-1. Examples of I2C Master Timer Period versus Speed Mode 1526 SPRUHE8E – October 2012 – Revised November 2019 List of Tables Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 76 24-1. Summary of Processor Mode, Privilege Level, and Stack Use 1607 ....................24-2. Processor Register Map 1608 ........... 24-3. Cortex General-Purpose Registers 0-12 (R0-R12) Field Descriptions 1609 List of Tables SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 77 25-30. Interrupt 128-133 Clear Pending (UNPEND4) Register Field Descriptions 1660 ..........25-31. Interrupt 0-31 Active Bit (ACTIVE0) Register Field Descriptions 1660 SPRUHE8E – October 2012 – Revised November 2019 List of Tables Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 78 25-57. MPU Region Base Address (MPUBASE) Register Field Descriptions 1689 ................... 25-58. Example SIZE Field Values 1689 ..........25-59. MPU Region Attribute and Size (MPUATTR) Field Descriptions 1690 List of Tables SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 79: Preface
For a complete listing of related documentation and development-support tools for these devices, visit the Texas Instruments website at http://www.ti.com. Additionally, the TMS320C28x CPU and Instruction Set Reference Guide (SPRU430) and TMS320C28x Floating Point Unit and Instruction Set Reference Guide (SPRUEO2) must be used in conjunction with this TRM.
Page 80: System Control And Interrupts
Code Security Module (CSM) ....................1.11 µCRC Module ............... 1.12 Inter Processor Communications (IPC) .................. 1.13 System Control Registers System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 81: Signal Description
VDD18. Pull low to enable the VREG18EN manual for pin Fixed Fixed Fixed internal 1.8-V voltage regulator (VREG18), pull high to disable VREG18. SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 82: System Control Functional Description
The master subsystem device identification registers are: DID0 and DID1. The control subsystem device identification registers are: PARTID, REVID, and CDID. System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 83: Device Configuration Registers
Table 1-3 shows various reset signals in this device and how it affects different hardware modules in the device. SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 84: Device Level Reset Sources
Please refer to the Boot ROM chapter for more details. Table 1-4 provides information for the device bring up time-line on power-up. System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 85: Device Bring-Up Time Line
It is recommended to connect both XRS and ARS pins together externally using a single trace. The internal reset which can pull ARS low is caused by the power-on reset (POR). SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 86 ROM. Refer to the Boot ROM chapter for more details on how boot ROM handles this reset. System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 87 ACIBRESET bit (bit 30) of the DEVICECNF register. Refer to the DEVICECNF register for details. SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 88 SRXRST. SRXRST is triggered by a master software reset or by a master debugger reset. SRXRST is also triggered by an XRS. Figure 1-1 shows reset connectivity on the device. System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 89: Resets Connectivity
C28x CLBISTRST SUBSYSTEM ‘0’ C28RSTIN C28SYSRST C28x SYNC DEGLITCH M3SSCLK C28x WDOG RESET INPUT SIGNAL STATUS C28NMIWD DEVICECNF REG SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 90: Handling Of Resets At System Level
Same as WDT1 reset above Same as MNMIWD above Master SRXRST, Software C28RSTIN reset Master SRXRST, Debugger C28RSTIN Reset System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 91 XRS reset, then boot ROM should not set clock dividers to default (for example, a debugger reset by the user while developing code on bench). SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 92 MRESC register which tells which C28NMI was unserviced that caused a reset. Unlike the master subsystem which has a reset cause register, the control subsystem does not. System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 93: Wir Mode
EMU0 and EMU1 pins can put the device in WIR mode. SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 94: Entering Wir Mode
Figure 1-2 shows how each boot ROM puts respective CPU in WIR mode. System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 95: Exiting Wir Mode
The user can then directly write a value other than the WIR_MODE_YES value (refer to Table 1-7) to these bits, and not set the sample bit. Therefore, when SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 96: Exceptions And Interrupts Control
IPC. This has to be taken care of by the user as per the application requirements. System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 97: Master Subsystem Exceptions Handling
For bus errors during fetches, even if the M3 sees an error response, it will not internally bus fault SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 98: Master Subsystem Non-Maskable Interrupt (Mnmi) Module
NMI to the Cortex-M3 on the master subsystem and the registers associated with them. System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 99: Master Subsystem Nmi Sources And Mnmiwd
The MNMIWD counter will stop counting and reset back to zero once all the set MNMIFLG bits and the NMIINT flag bit in the MNMIFLG register are cleared. SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 100 "0"), if the error condition that triggers this NMI occurs, the ACIBERR bit is set in the MNMIFLG register. This error is generated if a stuck condition is detected on the ACIB INTS or READY signals. System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 101: Control Subsystem Pie
(INT1 to INT12). Each of the 96 interrupts is supported by its own vector stored in a SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 102: Pie Interrupts Multiplexing
INTx.2 INTx.3 From INTx.4 INTx Peripherals or INTx.5 External INTx.6 Interrupts INTx.7 INTx.8 PIEACKx (Enable) (Flag) (Enable/Flag) PIEIERx(8:1) PIEIFRx(8:1) System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 103 CPU interrupt enable (IER) register or the debug interrupt enable register (DBGIER) and the global interrupt mask (INTM) bit. SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 104: Cpu Level Interrupt Handling
In this special case, the DBGIER is used and the INTM bit is ignored. If the DSP is in real-time mode and the CPU is running, the standard interrupt-handling process applies. System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 105: Enabling Interrupt
M0 and M1 memory blocks are treated as SARAM blocks and can be used freely without any restrictions. After a device reset operation, the vector table is mapped as shown in Table 1-11. SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 106: Control Subsystem C28X Processor After Reset Flow
C28x Mode 24x/240xA Source-Compatible C27x Object-Compatible 0 (Default at reset) The reset vector is always fetched from the boot ROM. System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 107: Pie Interrupt Sources And External Interrupts Xint1/Xint2/Xint3
PIE module also uses the PIEIER and PIEIFR registers to decode to which interrupt service routine the CPU should branch. SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 108 CPU IFR register, the following procedure should be followed: 1. Disable global interrupts (INTM = 1). 2. Set the EALLOW bit. System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 109: Multiplexed Interrupt Request Flow
The proper enable bit must be set (PIEIERx.y = 1) and b. The PIEACKx bit for the group must be clear. SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 110 No peripheral interrupts are assigned to the group. For example, PIE group 11 and 12 do not have any peripherals attached to them. System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 111: Pie Vector Table Mapping
Reset is always fetched from location 0x003F FFC0 in Boot ROM. All the locations within the PIE vector table are EALLOW protected. SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 112 Reserved INT1.4 0x0000 0D46 XINT1 INT1.5 0x0000 0D48 XINT2 INT1.6 0x0000 0D4A Reserved TINT0 (C28x Timer INT1.7 0x0000 0D4C System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 113 1 (highest) SPITXINTA (SPI- INT6.2 0x0000 0D92 INT6.3 0x0000 0D94 Reserved INT6.4 0x0000 0D96 Reserved MRINTA (McBSP- INT6.5 0x0000 0D98 SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 114 8 (lowest) PIE Group 11 Vectors -MUXed into CPU INT11 INT11.1 0x0000 0DE0 MTOCIPCINT1 1 (highest) INT11.2 0x0000 0DE2 MTOCIPCINT2 System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 115 The following events also clear an IFR flag: • The CPU acknowledges the interrupt. • The 28x device is reset. SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 116 For XINT1/XINT2/XINT3, there is also a 16-bit counter that is reset to 0x000 whenever an interrupt edge is detected. These counters can be used to accurately time stamp an occurrence of the interrupt. System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 117: Control Subsystem Exceptions Handling
Figure 1-9 explains how an NMI is generated to the control subsystem CPU. SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 118: Control Subsystem Nmi Sources And Cnmiwd
Control Subsystem NMI Sources This section explains the error events that can generate an NMI to the control subsystem CPU. System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 119 Real-Time Run-Free Mode When the CPU is in real-time run-free mode, the NMI watchdog counter operates as normal. SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 120: Safety Features
After modifying registers, they can once again be protected by executing the EDI instruction to clear the EALLOW bit. System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 121: Missing Clock Detection Logic
ISR for the NMI. If the CNMIWD expires it will generate a reset to the C28 CPU and C28 subsystem. SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 122: Reference Clock Limits For Detecting A Missing Clock
Ref Clock Frequency REFCLKLOLIMIT REFCLKHILIMIT 4 MHz (250ns) 10 MHz (100ns) 20 MHz (50ns) 0x11 100 MHz (10ns) 0x4E 0x52 System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 123: Missing Clock Detection Logic
4. C28 side PWMs tripped based on low limit configuration 1. Generate NMI to M3 and C28 CPU 2. Start both NMIWD counters SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 124: Pllslip Detection
In the event of a mismatch during a C28 NMI vector fetch, an NMI is generated to the M3 CPU. System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 125: Nmiwds
Please refer to the Watchdog Timers chapter for more details. SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 126: Ecc And Parity Enabled Rams, Shared Rams Protection
PLLSYSCLK. Refer to the Internal Memory chapter for more details on shared resources. System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 127: Clock Sources
If DCAN0 or DCAN1 is clocked from the XCLKIN source, then it cannot exceed 60 MHz. • If the USB is clocked from the XCLKIN source, then it cannot exceed 60 MHz. SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 128: Plls
– The final divider can then be programmed after a small delay determined by the system regulator and decoupling capacitors stabilize System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 129: Master Subsystem Clocking
USBPLL and CAN modules have the option to choose a clock source other than OSCCLK as shown in Figure 1-11. Refer to the respective sections for more details on USB and CAN clocking configurations. SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 131: Control Subsystem Clocking
Figure 1-12 shows the clocking control on the control subsystem. SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 132: Control Subsystem Clocks And Low Power Mode Configuration
Refer to Section 1.9 for more details on these registers. System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 133 PCLKCR3 registers. These registers are accessible only by the C28 CPU and are similar to earlier C2000 family of devices. Figure 1-13 shows various clock domain on the control subsystem. SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 134: Control Subsystem Peripherals Clocking
If this is done, the current drawn will be more than required. To avoid this, only enable the clocks required by the application. System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 135: Clocking Control Semaphore Functionality
It also cannot set the SEM bits to "0,1". Only the master SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 136: Acib And Analog Peripherals Clocking
1-12. Note that only the master subsystem can configure the XCLKOUT divider. Refer to the XPLLCLKCFG and CXCLK register descriptions for more details. System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 137: 32-Bit Cpu Timers 0/1/2
The timer registers are connected to the Memory Bus of the C28x processor. The timing of the CPU timers are synchronized to SYSCLKOUT of the processor clock. SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 138: Timerxtim Register (X = 0, 1, 2)
Figure 1-17. TIMERxTIMH Register (x = 0, 1, 2) TIMH R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 139: Timerxprd Register (X = 0, 1, 2)
This flag gets set when the CPU-timer decrements to zero. Writing a 1 to this bit clears the flag. SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 140: Timerxtpr Register (X = 0, 1, 2)
PSCH:PSC, and the TIMH:TIM decrements by one. TDDRH:TDDR also reloads the PSCH:PSC whenever the timer reload bit (TRB) is set by software. System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 141: Low Power Modes
Master Subsystem Low-Power Modes Configuration The master subsystem has the following low-power modes: • Sleep mode • Deep-sleep mode SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 142: M3 Subsystem Low-Power Modes
1.9.1.1.1.5). When the processor executes a WFI instruction, it stops executing instructions and enters sleep mode. See the Cortex™-M3 Instruction Set Technical User's Manual for more information. System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 143 M3 power modes, please refer to the Power Management Chapter of the Cortex™-M3 Technical Reference Manual. 1.9.1.2 Control Subsystem Low-Power Modes Configuration Table 1-26 summarizes the various low-power modes. SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 144: Low-Power Modes Configuration
QUALSTDBY bits (bits [7:2] of the CLPMCR0 register) . Refer to the GPIOs chapter for more details on the GPIOLPMSELx registers. System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 145: Code Security Module (Csm)
Each zone has its own 128 bit CSM password. The zone can be unsecured by executing the password match flow (PMF). Table 1-28 shows the levels of security. SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 146: Security Levels
NOTE: Access to the secure memory from the debuuger does not trip the debug probe. These accesses are just blocked and return ‘0’. System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 147 EXEONLY feature on flash sector A, which contains all of the security settings, for complete security initialization. SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 148: Csm Impact On Other On-Chip Resources
Register Name Reset Values Register Description 0x20-0000 Z1_CSMPSWD0 User Defined Low word (32-bit) of the 128-bit CSM password for zone1 System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 149: M3 Zone2 - Reserved Locations In Flash Memory
High word (32-bit) of the 128- bit CSM password 0x13-FFF4 ECSLPSWD0 User Defined Low word (32-bit) of the 64-bit CSM password SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 150 (PWL) followed by eight 16-bit (or four 32-bit) writes to CSMKEY registers. Figure 1-23 shows how PMF helps to initialize the security logic registers and disable security logic. System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 151: Csm Password Match Flow
Are CSM PWL = All Write the CSM Password of that zone into CSMKEY(0/1/2/3) registers Correct Password? Zone Unsecure SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 152 *CSM++ = 0x44443333; // Register CSMKEY1 at 0xAE2 *CSM++ = 0x66665555; // Register CSMKEY2 at 0xAE4 *CSM++ = 0x88887777; // Register CSMKEY3 at 0xAE6 System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 153: Zone Security Status
(PWL) followed by eight writes to KEY registers. Figure 1-24 shows how the PMF helps to initialize the security logic registers and disable security logic. SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 154: Ecsl Password Match Flow
Are ECSL PWL = All Write the ECSL Password of that zone into ECSLKEYx registers Correct Password? Zone ECSL Unlock System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 155 *ECSL++ = 0x44443333; // Register ECSLKEY1 at 0xAF2 Table 1-34 shows different conditions for any zone's ECSL to be secure or non-secure. SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 156: Do's And Don'ts To Protect Security Logic
CRC result for that perticual read. System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 157: Crc Polynomials
Refer to the Boot ROM chapter for more information on these IPC boot registers. SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 158: Msgrams
Message RAMs to build a software handshake mechanism between the two cores. Figure 1-25 shows the IPC flag messaging and interrupt mechanism. System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 159: Mtocipc Communication
CLR register on the M3 and the ACK register on the C28x. SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 160: Ctomipc Communication
(CTOMIPCINT1 to CTOMIPCINT4) to the M3 PIE if enabled. The remaining 28 bits (bit 4 to bit 31) can be used as explained above in a software-based handshake (flag/ack) mechanism. System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 161: Examples For Software Ipc Procedure
IPC Message registers that the master subsystem can use to convey a message to the control subsystem are given in Table 1-36. SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 162: Flash Pump Semaphore
M3 core cannot erase/program the M3 flash bank, but the M3 core can execute code and/or read data from the M3 flash bank. System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 163: Clock Configuration Semaphore
(a 2-bit field called SEM in CLKREQUEST registers). SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 164: Mastership Of Clock Configuration Registers For Different States Of Clock Configuration Semaphore
8. Put the PLL back into the clock path 9. Modify the clock dividers as desired by the application System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 165: Free Running Counter
If either core is executing, the counter runs. It is suggested that the user application should disable interrupts when reading the counters. SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 166: System Control Registers
GPIOHBCTL Performance Bus 0x6C MWRALLOW M3SYSRST Control Register Run Mode Clock RCGC0 Gating Control 0x100 MWRALLOW M3SYSRST Register 0 System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 167 Configuration Serial Port Loop Back SERPLOOP 0x08 MWRALLOW M3SYSRST Control Register Master Subsystem: MCIBSTATUS 0x0C SRXRST ACIB Status Register SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 168 Reference Limit 0X40 MWRALLOW Register XPLL CLKOUT XPLLCLKCFG 0X50 MWRALLOW Control Register Control Subsystem: CCLKOFF Clock Disable 0X60 MWRALLOW Register System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 169 Control Subsystem Peripheral Clocking Control 0x7000 Registers: C28 Reset Cause CRESC 0x2C EALLOW Register C28 XCLKOUT CXCLK 0x10 EALLOW C28SYSRST control register SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 170 C28 XINT2 Counter XINT2CTR 0x09 C28SYSRST Register C28 XINT3 Counter XINT3CTR 0x0A C28SYSRST Register Master Subsystem CSM 0x400F: Configuration Registers B400 System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 171 0x15 C28SYSRST Register for C28x 0x400FB6 µCRC Configuration Register µCRC Configuration µCRCCONFIG M3SYSRST Register µCRCCONTR µCRC Control M3SYSRST Register SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 172 C28SYSRST, CTOMIPCSET 0x00 request set register SRXRST C28 to M3 core IPC C28SYSRST, CTOMIPCCLR 0x02 request clear register SRXRST System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 173 EALLOW MWRALLOW SRXRST request register Clock configuration CCLKREQUES semaphore C28 0x26 EALLOW MWRALLOW SRXRST request register Reserved Reserved 0x28 SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 174: Device Identification And Device Configuration
Package Pin Count 289 pins 12-8 Reserved Reserved TEMP Temperature Range Extended Industrial Temperature Range (-40°C to 105°C). PACKAGE Package Type System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 175: Device Configuration 1 (Dc1) Register
WDT0 is present Reserved Reserved JTAG JTAG Debugger Interface JTAG debugger interface is not present JTAG debugger interface is present SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 176: Device Configuration 2 (Dc2) Register
II2C0 Whether I2C0 is present or not depends on the device configuration. I2C0 is not present I2C0 is present System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 177 UART0 Whether UART0 is present or not depends on the device configuration. UART0 is not present UART0 is present. SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 178: Device Configuration 4 (Dc4) Register
Whether GPIOG is present or not depends on the device configuration. GPIO PortG is not present GPIO PortG is present System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 179 Whether GPIOA is present or not depends on the device configuration. GPIO PortA is not present GPIO PortA is present SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 180: Device Configuration 6 (Dc6) Register
Whether CAN0 is present or not depends on the device configuration. CAN0 is not present CAN0 is present 23-1 Reserved Reserved System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 181: Device Configuration 7 (Dc7) Register
OTP flash. GPIO Port S is not present GPIO Port S is present SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 182 OTP flash. GPIO Port E is not present GPIO Port E is present System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 183: Master Subsystem Configuration (Mcnf) Register
Reserved µCRC µCRC Configuration µCRC is disabled µCRC is present Reserved Reserved FLASH M3 Flash Size Configuration 512KB 256KB SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 184: Serial Port Loop Back Control (Serploop) Register
Reading this bit gives the power state of the Analog Subsystem. Analog subsystem power not present Analog subsystem power present System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 185: C28 Device Part Id (Partid) Register
Table 1-53. C28 Device ID (CDID) Register Field Descriptions Field Value Description 15-8 CLASS Device class. Concerto class device. Device family. Concerto family of microcontrollers. SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 186: Control Subsystem Device Configuration (Devicecnf) Register
R-0:0 Reserved Reserved HRPWM R-0:0 R-0:0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 187: Control Subsystem Peripheral Configuration 1 (Ccnf1) Register
Configuration When set, this enables the respective eCAP module. Respective eCAP module is disabled Respective eCAP module is enabled SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 188: Control Subsystem Peripheral Configuration 2 (Ccnf2) Register
EPWM10 module is enabled EPWM9 ePWM9 Configuration. When set, this enables the ePWM9 module. ePWM9 module is disabled ePWM9 module is enabled System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 189: Control Subsystem Peripheral Configuration 3 (Ccnf3) Register
When set, this enables the C28 DMA module. C28 DMA module is disabled C28DMA module is enabled 10-0 Reserved Reserved SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 190: Control Subsystem Peripheral Configuration 4 (Ccnf4) Register
Reserved Reserved S7-0 S7-0 Shared Memory Configuration S7-0 Shared RAM configuration. S7-0 RAM is disabled S7-0 RAM is enabled System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 191: Reset Control And Status Registers
Note: This flag is 2 bits to take care of any error conditions that may cause inadvertent setting of a single bit flag; SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 192 15-1 Reserved Reserved CRES C28 Reset Status Bit C28 CPU is in reset C28 CPU is out of reset System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 193: Master Reset Cause (Mresc) Register
If set to 11, indicates that M3 CPU HWBIST has run to completion and issued a reset to the M3 CPU. SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 194: C28 Reset Cause Register (Cresc) Register
If ‘0’ then there was no C28 NMI WDOG reset since the previous POR Clears this bit. No effect System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 195: Software Reset Control 0 (Srcr0) Register
When this bit is set, Watchdog Timer module 0 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. Reserved Reserved SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 196: Software Reset Control 1 (Srcr1) Register
When this bit is set, SSI3 is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 197: Software Reset Control 2 (Srcr2) Register
When this bit is set, EMAC is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. 27-17 Reserved Reserved SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 198: Software Reset Control 3 (Srcr3) Register
R/W-0 R/W-0 R-0:0 Reserved UART4 R-0:0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 199: General-Purpose Input/Output Software Reset Control (Srgpio) Register
When this bit is set, GPIOM is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 200 When this bit is set, GPIOA is reset. All internal data is lost and the registers are returned to their reset states. This bit must be manually cleared after being set. System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 201: Wirmode Registers
Reading this bit will give the state of the EMU1 pin on reset or when sampled. Has no effect Forces the bit to "1" SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 202: Exception And Interrupts
ROM. This is a write once bit, once set it cannot be cleared until a system reset. NMI disabled NMI enabled System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 203: M3Nmi Flag (Mnmiflg) Register
NMIFLGCLR register or by an XRS reset. No CLOCKFAIL condition pending CLOCKFAIL condition generated SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 204: M3Nmi Flag Clear (Mnmiflgclr) Register
Note 2: Users should clear the pending FAIL flag first and then clear the NMIINT flag. System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 205: M3Nmi Flag Force (Mnmiflgfrc) Register
Writing a 1 to these bits will set the respective FAIL flag in the NMIFLG and NMISHDFLG registers. SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 206: M3Nmi Watchdog Counter (Mnmiwdcnt) Register
Writing a PERIOD value that is smaller then the current counter value will automatically force an NMIRS to the M3 and hence reset the watchdog counter. System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 207: C28 Nmi Configuration (Cnmicfg) Register
NOTE: The C28NMIFLG register is only reset by the XRS signal and not the C28 SYSRS signal. This is so the cause of the particular reset condition can be identified. SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 208: C28 Nmi Flag (Cnmiflg) Register
No further NMI interrupts pulses are generated until this flag is cleared by the user. No NMI interrupt generated NMI interrupt generated System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 209: C28 Nmi Flag Clear (Cnmiflgclr) Register
NMIINT NMI Interrupt Flag Clear Ignored; always reads back 0. Clears the corresponding flag bit in the NMIFLG register. SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 210: C28 Nmi Flag Force (Cnmiflgfrc) Register
If no enabled "NMI" flag is set, then the counter will reset to zero and remain at zero until an enabled "NMI" flag is set. System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 211: C28 Nmi Watchdog Period (Cnmiwdprd) Register
Reserved PIEACK R/W1C-1 LEGEND: R/W1C = Read/Write 1 to clear; R = Read only; -n = value after reset SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 212: Pie, Intx Group Enable Register (Pieierx) (X = 1 To 12)
NOTE: Care must be taken when clearing PIEIER bits during normal operation. See Section Section 1.5.4.3.2 for the proper procedure for handling these bits. System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 213: Pie, Intx Group Flag Register (Pieifrx) (X = 1 To 12)
The following events also clear an IFR flag: • The CPU acknowledges the interrupt. • The 28x device is reset. SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 214: Cpu Interrupt Flag Register (Ifr)
At least one INT6 interrupt is pending. Write a 0 to this bit to clear it to 0 and clear the interrupt request System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 215 When using the OR IER and AND IER instructions to modify IER bits make sure they do not modify the state of bit 15 (RTOSINT) unless a real-time operating system is present. SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 216: Cpu Interrupt Enable Register (Ier)
Interrupt 7 enable. INT7 enables or disables CPU interrupt level INT7. Level INT7 is disabled Level INT7 is enabled System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 217: Debug Interrupt Enable Register (Dbgier)
Data logging interrupt enable. DLOGINT enables or disables the CPU data logging interrupt Level INT6 is disabled Level INT6 is enabled SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 218 INT1 Interrupt 1 enable.INT1 enables or disables CPU interrupt level INT1. Level INT1 is disabled Level INT1 is enabled System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 219: C28 External Interrupt 1 Configuration Register (Xint1Cr)
Reserved POLARITY Rsvd ENABLE R/W-0:0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 220: C28 External Interrupt 1 Counter Register (Xint1Ctr)
The counter is a read only register and can only be reset to zero by a valid interrupt edge or by the C28 SYSRSN reset. System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 221: C28 External Interrupt 3 Counter Register (Xint3Ctr)
System PLL is powered off; clock to the system is a direct feed from X1. System PLL is enabled and clock to the system will depend on SYSPLLMULT and SYSPLLCLKEN register bit configuration. SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 222: Safety Control Registers
Figure 1-89. M3 Configuration Lock (MLOCK) Register Reserved MSxMSELLOCK R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 223: Missing Clock Status (Mclksts) Register
R-0:0 R/W-0 Reserved REFCLKOFF R-0:0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 224: Missing Clock Enable (Mclken) Register
Reserved R-0:0 REFCLKHILIMIT REFCLKLOLIMIT R/W-0x7A R/W-0x2 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 225: C28 User_Swreg1 Register
Table 1-106. C28_USER_SWREG2 Register Field Descriptions Field Value Description Reserved Reserved 14-9 SWREG2 General purpose register for C28 software use. Reserved Reserved SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 226: Clocking Control Registers
Reserved R-0x1 Reserved SYSDIVSEL R-0:0 R/W-11 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 227: System Pll Lock Status (Syspllsts) Register
Figure 1-99. Master Subsystem Clock Divider (M3SSDIVSEL) Register Reserved M3SSDIVSEL R-0:0 R/W-10 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 228: Xpll Clkout Control (Xpllclkcfg) Register
USB PLL is bypassed; clock to the USB is direct feed from GPIO_XCLKIN. USB PLL is on the clock path to USBCLK and it is the PLL multiplied clock. System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 229: Usb Pll Multiplier (Upllmult) Register
Integer multiplier = 2 000010 Integer multiplier = 3 000011 Integer multiplier = 4 … … 111111 Integer multipler = 63 SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 230: Usb Pll Lock Status (Upllsts) Register
Figure 1-105. Bit Clock Source Selection for CAN1 (CAN1BCLKSEL) Register Reserved BCLKSEL R-0:0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 231: Run Mode Clock Configuration (Rcc) Register
PORT J AHB. This bit defines the memory aperture for Port J Advanced Peripheral Bus (APB). This bus is the legacy bus. Advanced High-Performance Bus (AHB) SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 232: Run Mode Clock Gating Control Register 0 (Rcgc0)
Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the module generates bus faults. Reserved Reserved System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 233: Sleep Mode Clock Gating Control Register 0 (Scgc0)
Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the module generates bus faults. Reserved Reserved SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 234: Run Mode Clock Gating Control Register 1 (Rcgc1)
Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the module generates bus faults. System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 235: Sleep Mode Clock Gating Control Register 1 (Scgc1)
Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the module generates bus faults. 29-20 Reserved Reserved SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 236 Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the module generates bus faults. System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 237: Deep Sleep Mode Clock Gating Control Register 1 (Dcgc1)
Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the module generates bus faults. SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 238: Run Mode Clock Gating Control Register 2 (Rcgc2)
Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the module generates bus faults. 27-17 Reserved Reserved System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 239 Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the module generates bus faults. SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 240: Sleep Mode Clock Gating Control Register 2 (Scgc2)
Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the module generates bus faults. System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 241 Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the module generates bus faults. SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 242: Deep Sleep Mode Clock Gating Control Register 2 (Dcgc2)
Otherwise, it is unclocked and disabled. If the module is unclocked, reads or writes to the module generates bus faults. System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 243: Run Mode Clock Gating Control Register 3 (Rcgc3)
R/W-0 R-0:0 Reserved UART4 R-0:0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 244: Deep Sleep Mode Clock Gating Control Register 3 (Dcgc3)
When enabled, the GPIO module is provided a clock and accesses to registers are allowed. When disabled, the clock is disabled to save power and accesses to module registers generate a bus fault. System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 245: General-Purpose Run Mode Clock Gating Control Register (Rcgcgpio)
GPIO modules in SLEEP mode. When enabled, the GPIO module is provided a clock. When disabled, the clock is disabled to save power. SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 246: General-Purpose Sleep Mode Clock Gating Control Register (Scgcgpio)
GPIO modules in DEEP SLEEP mode. When enabled, the GPIO module is provided a clock. When disabled, the clock is disabled to save power. System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 247: General-Purpose Deep-Sleep Mode Clock Gating Control Register (Dcgcgpio)
1.13.7.28 Deep Sleep Clock Configuration (DSLPCLKCFG) Register NOTE: M3 Watchdog 1 will be clocked by the deep sleep clock selected by the DSLPCLKCFG.DSOSCSRC bits. SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 248: Deep Sleep Clock Configuration (Dslpclkcfg) Register
Use the 32-kHz clock as the clock source Use the 10-MHz ATOB clock as the clock source 0x3-0x7 Reserved Reserved Reserved System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 249: C28 Cpu Timer 2 Clock Configuration (Clkctl) Register
HRPWMENCLK R-0:0 R/W-0 R-0:0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 250: Peripheral Clock Control Register 1 (Pclkcr1)
(n = 6-1) When set, this enables the clock to the respective eCAP module. Clock is disabled Clock is enabled System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 251: Peripheral Clock Control Register 2 (Pclkcr2)
Clock Enable When set, this enables the clock to the ePWM9 module. ePWM9 clock is disabled ePWM9 clock is enabled SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 252: Peripheral Clock Control Register 3 (Pclkcr3)
When set, this enables the clock to the CPU timers on the C28 subsystem. (n = 2-0) Timer clock is disabled Timer clock is enabled Reserved Reserved System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 253: High-Speed Clock Prescaler (Chispcp) Register
LSPCLK = SYSCLKOUT / 8 LSPCLK = SYSCLKOUT / 10 LSPCLK = SYSCLKOUT / 12 LSPCLK = SYSCLKOUT / 14 SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 254: C28 Xclkout Divider Register (Cxclk)
SYSCLKOUT. The ratios are given below. XCLKOUT = C28 SYSCLKOUT/4 XCLKOUT = C28 SYSCLKOUT/2 XCLKOUT = C28 SYSCLKOUT XCLKOUT = Off System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 255: Master Subsystem Code Security Module (Csm) Registers
Figure 1-135. Z1_CSMKEY3 Register CSMKEY R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 256: Z1_Ecslkey0 Register
Value Description 31-0 CSMKEY To unlock M3 zone2, write the same value in CSMPSWD0 of zone2 to this register. System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 257: Z2_Csmkey1 Register
Figure 1-142. Z2_ECSLKEY0 Register ECSLKEY R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 258: Z2_Ecslkey1 Register
Dummy read to M3-Zone1 CSM PWL (Password locations) have not been performed. Dummy read to M3-Zone1 CSM PWL (Password locations) have been performed. System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 259: Z2_Csmcr Register
R=0/W=1 CSM-ALLONE ECSL- CSM-ALLZERO Reserved ALLZERO LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 260: Z2_Csmcr Register Field Descriptions
CSM Passwords of M3 Zone2 does not contain all 0's CSM Passwords of M3 Zone2 contains all 0's Reserved Reserved System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 261: Z1_Grabsectr Register
Request to allocate M3 Flash Sector F to M3 Zone1 Request to allocate M3 Flash Sector F to M3. Zone1 Request to make M3 Flash Sector F Non-Secure SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 262 Request to allocate M3 Flash Sector M to M3 Zone1 Request to allocate M3 Flash Sector M to M3 Zone1 Request to make M3 Flash Sector M Non-Secure System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 263: Z1_Grabramr Register
GRABSECTL GRABSECTM R-00 R-00 R-00 R-00 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 264: Z2_Grabsectr Register
Request to allocate M3 Flash Sector I to M3 Zone2 Request to allocate M3 Flash Sector I to M3 Zone2 Request to make M3 Flash Sector I Non-Secure System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 265: Z2_Grabramr Register
Request to allocate M3 C1 RAM to M3 Zone2 Request to allocate M3 C1 RAM to M3 Zone2 Request to make M3 C1 RAM Non-Secure SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 266 Request to allocate M3 C0 RAM to M3 Zone2 Request to allocate M3 C0 RAM to M3 Zone2 Request to make M3 C0 RAM Non-Secure System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 267: Z1_Exeonlyr Register
Execute only select register sector J Execute-only is enabled for Sector J on Zone 1 Execute-only disabled for Sector J on Zone 1 SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 268: Z2_Exeonlyr Register
Execute only select register Sector E Execute-only is enabled for Sector E on Zone 2 Execute-only is disabled for Sector E on Zone 2 System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 269: Otpseclock Register
µCRC does not have ability to calculate CRC on secured memories (including EXE-Only flash sectors). µCRC has the ability to calculate CRC on M3 secured memories (including EXE-Only flash sectors) SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 270 JTAG Port is enabled. Debugger (for example, CCS) can be connected to the Cortex-M3 as well as the C28x. System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 271: Control Subsystem Code Security Module (Csm) Registers
Figure 1-156. CSMKEY3 Register CSMKEY R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 272: Csmcr Register
Dummy read to control subsystem CSM PWL (Password locations) have not been performed. Dummy read to control subsystem CSM PWL (Password locations) have been performed. System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 273: Ecslkey0 Register
To disable ECSL logic active on the control subsystem, the user needs to write the same value in ECSLPSWD1 of zone1 to this register. SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 274: Exeonlyr Register
Execute-Only protection is disabled for C28x Flash Sector F (only if it is allocated to the control subsystem) System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 275: Μcrc Register Description
Table 1-172. µCRC Register Summary Name Address (Offset) Size (X32) Description µCRCCONFIG µCRC Configuration Register µCRCCONTROL µCRC Control Register SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 276: Μcrcconfig Register
Figure 1-163. µCRCRES Register RESULT R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 277: Master Subsystem Ipc Registers
MTOCIPCFLG is set. The status of this bit is not readable in this register – it is readable in the MTOCIPCFLG and STS registers. SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 278 MTOCINT1 is raised to the C28 PIE. The status of this bit is not readable in this register – it is readable in the corresponding bit in the MTOCIPCFLG and STS registers. System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 279: M3 To C28 Ipc Clear (Mtocipcclr) Register
MTOCIPCFLG is cleared. The status of this bit is not readable in this register – it is readable in the MTOCIPCFLG and STS registers. SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 280 MTOCIPCFLG is cleared. The status of this bit is not readable in this register – it is readable in the MTOCIPCFLG and STS registers. System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 281: M3 To C28 Core Flag (Mtocipcflg) Register
MTOCIPCSET bit has been written with a ‘1’ and MTOCIPCCLR or MTOCIPCACK bit has not been written with a ‘1." SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 282 MTOCIPCSET bit has been written with a ‘1’ and MTOCIPCCLR or MTOCIPCACK bit has not been written with a ‘1." System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 283: M3 To C28 Core Ipc Acknowledge (Ctomipcack) Register
CTOMIPCFLG and CTOMIPCSTS to ‘0’. The status of this bit is not readable in this register – it is readable in the CTOMIPCFLG and STS registers. SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 284 CTOMIPCFLG and CTOMIPCSTS to ‘0’. The status of this bit is not readable in this register – it is readable in the CTOMIPCFLG and STS registers. System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 285: C28 To M3 Core Ipc Status (Ctomipcsts) Register
CTOMIPCSET bit has been written with a ‘1’ and CTOMIPCCLR or CTOMIPCACK bit has not been written with a ‘1." SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 286 CTOMIPCSET bit has been written with a ‘1’ and CTOMIPCCLR or CTOMIPCACK bit has not been written with a ‘1." System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 287: M3 Flash Semaphore Register
• State transitions from "00" → "11" and "11" → "00" are allowed by design. However these transitions will not result in change in ownership. SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 288: Control Subsystem Ipc Registers
IPC6 IPC5 IPC4 IPC3 IPC2 IPC1 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 289: Ctomipcset Register Field Descriptions
CTOMIPCFLG is set. The status of this bit is not readable in this register – it is readable in the CTOMIPCFLG and STS registers. SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 290 IPC6 IPC5 IPC4 IPC3 IPC2 IPC1 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 291: Ctomipcclr Register
CTOMIPCFLG is cleared. The status of this bit is not readable in this register – it is readable in the CTOMIPCFLG and STS registers. SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 292 IPC6 IPC5 IPC4 IPC3 IPC2 IPC1 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 293: Ctomipcflg Register
CTOMIPCSET bit has been written with a ‘1’ and CTOMIPCCLR or CTOMIPCACK bit has not been written with a ‘1’. SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 294 IPC6 IPC5 IPC4 IPC3 IPC2 IPC1 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 295: Mtocipcack Register
MTOCIPCFLG and MTOCIPCSTS to ‘0’. The status of this bit is not readable in this register – it is readable in the MTOCIPCFLG and STS registers. SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 296 IPC6 IPC5 IPC4 IPC3 IPC2 IPC1 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 297: Mtocipcsts Register
MTOCIPCSET bit has been written with a ‘1’ and MTOCIPCCLR or MTOCIPCACK bit has not been written with a ‘1’. SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 298: C28 Flash Semaphore Register
Writing the value 0x4CE7395 will allow writes to the SEM bits or writes are ignored. Reads will return 0. Note: This is to prevent spurious writes to the semaphore bits. Reserved Reserved System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 299: C28 Clock Semaphore Register
• State transitions from "00" → "11" and "11" → "00" are allowed by design. However these transitions will not result in change in ownership. SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 300: Master And Control Subsystem Ipc Registers
IPC commands from the C28 to the M3 CPU. It is read/write for the C28 CPU and read only for the M3 CPU. System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 301: Ctomipcaddr Register
Figure 1-184. MTOCIPCCOM Register COMMAND R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 302: Mtocipccom Register Field Descriptions
IPC commands from the M3 to the C28 CPU. It is read/write to the M3 CPU and read only to the C28 CPU. System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 303: Mtocipcaddr Register
Figure 1-188. CTOMIPCBOOTSTS Register BOOTSTS R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUHE8E – October 2012 – Revised November 2019 System Control and Interrupts Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 304: Mtocipcbootmoderegister
C28 boot mode to enter. It is read/write to the M3 CPU and read only to the C28 CPU. System Control and Interrupts SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 305: M3 General-Purpose Timers
Page ....................GPTM Features ....................Block Diagram ..................Functional Description ................Initialization and Configuration ....................Register Map ..................Register Descriptions SPRUHE8E – October 2012 – Revised November 2019 M3 General-Purpose Timers Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 306: Gptm Features
Detect Odd CCPPin GPTMTBMR TB Comparator GPTMTBILR GPTMTBMATCHR Timer B Free-Running GPTMTBPR Value GPTMTBPMR 0x0000 (DownCounterModes) 0xFFFF (UpCounterModes) System Clock M3 General-Purpose Timers SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 307: Functional Description
(GPTMTAV) register and the GPTM Timer B Value (GPTMTBV) register. The prescale counters are initialized to 0x00: the GPTM Timer A Prescale (GPTMTAPR) register, and the GPTM Timer B Prescale (GPTMTBPR) register . SPRUHE8E – October 2012 – Revised November 2019 M3 General-Purpose Timers Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 308: Timer Modes
Table 2-3. 16-Bit Timer With Prescaler Configurations Prescale #Clock (Tc) Max Time Units 00000000 0.6554 00000001 1.3107 00000010 1.9661 ------------ M3 General-Purpose Timers SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 309: Timer Daisy Chain
If the TASTALL and/or TBSTALL bits in the GPTMCTL register are set, the timer does not freeze if the RTCEN bit is set in GPTMCTL. SPRUHE8E – October 2012 – Revised November 2019 M3 General-Purpose Timers Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 310: Edge-Count Mode Example
Figure 2-3. Edge-Count Mode Example Timer stops, Timer reload flags on nextcycle Ignored Ignored Count asserted 0x000A 0x0009 0x0008 0x0007 0x0006 Input Signal M3 General-Purpose Timers SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 311: 16-Bit Input Edge-Time Mode Example
GPTMTnR=X GPTMTnR=Y GPTMTnR=Z 0xFFFF Time Input Signal 2.3.2.5 PWM Mode NOTE: The prescaler is not available in 16-Bit PWM mode. SPRUHE8E – October 2012 – Revised November 2019 M3 General-Purpose Timers Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 312: Dma Operation
No other special steps are needed to enable Timers for µDMA operation. Refer to the Micro Direct Memory Access (µDMA) chapter for more details about programming the µDMA controller. M3 General-Purpose Timers SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 313: Accessing Concatenated Register Values
8. Poll the GPTMRIS register or wait for the interrupt to be generated (if enabled). In both cases, the status flags are cleared by writing a 1 to the appropriate bit of the GPTM Interrupt Clear Register (GPTMICR). SPRUHE8E – October 2012 – Revised November 2019 M3 General-Purpose Timers Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 314: Real-Time Clock (Rtc) Mode
5. Load the timer start value into the GPTM Timer n Interval Load (GPTMTnILR) register. 6. If interrupts are required, set the CnEIM bit in the GPTM Interrupt Mask (GPTMIMR) register. M3 General-Purpose Timers SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 315: 16-Bit Pwm Mode
GPTM Masked Interrupt 0x020 GPTMMIS 0x0000.0000 Status 0x024 GPTMICR 0x0000.0000 GPTM Interrupt Clear GPTM Timer A Interval 0x028 GPTMTAILR 0xFFFF.FFFF Load SPRUHE8E – October 2012 – Revised November 2019 M3 General-Purpose Timers Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 316: Register Descriptions
GPTMCFG register. When in PWM mode, set the TAAMS bit , clear the TACMR bit, and configure the TAMR field to 0x2. M3 General-Purpose Timers SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 317: Gptm Timer A Mode (Gptmtamr) Register
GPTM Timer A Mode. The timer mode is based on the timer configuration defined by bits 2:0 in the GPTMCFG register Reserved One-Shot Timer mode Periodic Timer mode Capture mode SPRUHE8E – October 2012 – Revised November 2019 M3 General-Purpose Timers Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 318: Gptm Timer B Mode (Gptmtbmr) Register, Offset 0X008
Note: To enable PWM mode, you must also clear the TBCMR bit and configure the TBMR field to 0x1 or 0x2. TBCMR GPTM Timer B Capture Mode Edge-Count mode Edge-Time mode M3 General-Purpose Timers SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 319: Gptm Control (Gptmctl) Register, Offset 0X00C
Timer B is enabled and begins counting or the capture logic is enabled based on the GPTMCFG register. Reserved Reserved SPRUHE8E – October 2012 – Revised November 2019 M3 General-Purpose Timers Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 320: Gptm Interrupt Mask (Gptmimr) Register, Offset 0X018
GPTM Timer B Mode Match Interrupt Mask Interrupt is disabled. Interrupt is enabled. CBEIM GPTM Capture B Event Interrupt Mask Interrupt is disabled. Interrupt is enabled. M3 General-Purpose Timers SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 321: Gptm Raw Interrupt Status (Gptmris) Register, Offset 0X01C
The TBMIE bit is set in the GPTMTBMR register, and the match value in the GPTMTBMATCHR register has been reached when in the one-shot and periodic modes. SPRUHE8E – October 2012 – Revised November 2019 M3 General-Purpose Timers Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 322: Gptm Masked Interrupt Status (Gptmmis) Register, Offset 0X020
TBTOMIS Reserved TAMMIS RTCMIS CAEMIS CAMMIS TATOMIS LEGEND: R/W = Read/Write; R = Read only; -n = value after reset M3 General-Purpose Timers SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 323: Gptm Interrupt Clear (Gptmicr) Register, Offset 0X024
The GPTM Interrupt Clear (GPTMICR) register is used to clear the status bits in the GPTMRIS and GPTMMIS registers. Writing a 1 to a bit clears the corresponding bit in the GPTMRIS and GPTMMIS registers. SPRUHE8E – October 2012 – Revised November 2019 M3 General-Purpose Timers Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 324: Gptm Interrupt Clear (Gptmicr) Register
16-bit mode, the upper 16 bits of this register read as 0s and have no effect on the state of GPTMTBILR. M3 General-Purpose Timers SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 325: Gptm Timer A Interval Load (Gptmtailr) Register
In a 16-bit mode, the upper 16 bits of this register read as 0s and have no effect on the state of GPTMTBMATCHR. SPRUHE8E – October 2012 – Revised November 2019 M3 General-Purpose Timers Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 326: Gptm Timer A Match (Gptmtamatchr) Register
Figure 2-18. GPTM Timer A Prescale (GPTMTAPR) Register Reserved TAPSR R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset M3 General-Purpose Timers SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 327: Gptm Timer A Prescale (Gptmtbpr) Register
The GPTM Timer B Prescale Match (GPTMTBPMR) register effectively extends the range of GPTMTBMATCHR to 24 bits when operating in 16-bit one-shot or periodic mode. SPRUHE8E – October 2012 – Revised November 2019 M3 General-Purpose Timers Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 328: Gptm Timer B Prescale Match (Gptmtbpmr) Register
Input Edge Count, Input Edge Time, and PWM modes, which is the upper 8 bits of the count. Bits 31:24 are reserved in both cases. M3 General-Purpose Timers SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 329: Gptm Timer B (Gptmtbr) Register
23:16 contain the current, free-running value of the prescaler, which is the upper 8 bits of the count. Bits 31:24 are reserved in both cases. SPRUHE8E – October 2012 – Revised November 2019 M3 General-Purpose Timers Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 330: Gptm Timer B Value (Gptmtbv) Register
A read returns the current, free-running value of Timer A in all modes. When written, the value written into this register is loaded into the GPTMTAR register on the next clock cycle. M3 General-Purpose Timers SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 331: Spruhe8E - October 2012 - Revised November 2019
........................... Topic Page ..................... Introduction ....................Register Map ..................Register Descriptions SPRUHE8E – October 2012 – Revised November 2019 M3 Watchdog Timers Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 332: Watchdog Timer Module Block Diagram
System Clock/ WDTTEST OSCCLK Comparator WDTVALUE Identification Registers WDTPCellID0 WDTPeriphID0 WDTPeriphID4 WDTPCellID1 WDTPeriphID1 WDTPeriphID5 WDTPCellID2 WDTPeriphID2 WDTPeriphID6 WDTPCellID3 WDTPeriphID3 WDTPeriphID7 M3 Watchdog Timers SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 333 Note that the watchdog timer module clock must be enabled before the registers can be programmed. See the System Control chapter, Run Mode Clock Gating Control Register 0 (RCGC0) section. SPRUHE8E – October 2012 – Revised November 2019 M3 Watchdog Timers Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 334: Watchdog Load (Wdtload) Register
Value Description 31-0 WDTLOAD Watchdog load value Register not written. Value not loaded. Register written. Vlaue loaded and counter restarts. M3 Watchdog Timers SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 335: Watchdog Value (Wdtvalue) Register
Table 3-3. Watchdog Value (WDTVALUE) Register Field Descriptions Field Value Description 31-0 WDTVALUE Watchdog value. Current value of the 32-bit down counter. SPRUHE8E – October 2012 – Revised November 2019 M3 Watchdog Timers Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 336: Watchdog Control (Wdtctl) Register
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Table 3-5. Watchdog Interrupt Clear (WDTICR) Register Field Descriptions Field Value Description 31-0 WDTINTCLR Watchdog interrupt clear M3 Watchdog Timers SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 337: Watchdog Raw Interrupt Status (Wdtris) Register
The watchdog has not timed out or the watchdog timer interrupt is masked. A watchdog time-out event has been signalled to the interrupt controller. SPRUHE8E – October 2012 – Revised November 2019 M3 Watchdog Timers Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 338: Watchdog Test (Wdttest) Register
A read of this register returns the following values: A watchdog time-out event has been signalled to the interrupt controller. 0x0000. Locked 0001 0x0000. Unlocked 0000 M3 Watchdog Timers SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 339: Watchdog Peripheral Identification 4 (Wdtperiphid4) Register
Table 3-12. Watchdog Peripheral Identification 6 (WDTPeriphID6) Register Field Descriptions Field Value Description 31-8 Reserved Reserved PID6 WDT Peripheral ID Register [23:16] SPRUHE8E – October 2012 – Revised November 2019 M3 Watchdog Timers Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 340: Watchdog Peripheral Identification 7 (Wdtperiphid7) Register
Table 3-15. Watchdog Peripheral Identification 1 (WDTPeriphID1) Register Field Descriptions Field Value Description 31-8 Reserved Reserved PID1 WDT Peripheral ID Register [15:8] M3 Watchdog Timers SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 341: Watchdog Peripheral Identification 2 (Wdtperiphid2) Register
Table 3-18. Watchdog PrimeCell Identification 0 (WDTPCellID0) Register Field Descriptions Field Value Description 31-8 Reserved Reserved CID0 Watchdog PrimeCell ID Register [7:0] SPRUHE8E – October 2012 – Revised November 2019 M3 Watchdog Timers Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 342: Watchdog Primecell Identification 1 (Wdtpcellid1) Register
Table 3-21. Watchdog PrimeCell Identification 3 (WDTPCellID3) Register Field Descriptions Field Value Description 31-8 Reserved Reserved CID3 Watchdog PrimeCell ID Register [31:24] M3 Watchdog Timers SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 343 See the General-Purpose Input/Output (GPIO) and C28 General-Purpose Input/Output (GPIO) sections of this chapter for more information..........................Topic Page ..............General-Purpose Input/Output (GPIO) ............C28 General-Purpose Input/Output (GPIO) SPRUHE8E – October 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 344 Important: All GPIO pins are configured as GPIOs and tri-stated by default (GPIOAFSEL=0, GPIODEN=0, GPIOPUR=0, and GPIOPCTL=0). A Power-On-Reset (POR) or asserting XRS puts the pins back to their default state. General-Purpose Input/Output (GPIO) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 345: Gpio Pins And Alternate Functions
MII_COL SSI0Rx CAN1Rx USB0PFLT PD2_GPIO1 U1Rx CCP6 CCP5 EPI0S20 SSI0Clk U1Tx CAN0Rx PD3_GPIO1 U1Tx CCP7 CCP0 EPI0S21 SSI0Fss U1Rx CAN0Tx SPRUHE8E – October 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 346 U4Rx MII_TXCK PG1_GPIO4 U2Tx I2C1SDA ODISCHRG EPI0S14 MII_RXD1 U4Tx MII_TXER VBUS PG2_GPIO4 USB0DM MII_COL OCHRGVB PG3_GPIO4 MII_CRS ODMPULLD MII_RXDV TRACED1 General-Purpose Input/Output (GPIO) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 347 PJ6_GPIO6 EPI0S30 CCP1 MII_PHYINT U2Rx MII_RXER PJ7_GPIO6 CCP0 MII_PHYRS U2Tx MII_RXCK 3/XCLKIN PK0_GPIO7 SSI0Tx PK1_GPIO7 SSI0Rx PK2_GPIO7 SSI0Clk PK3_GPIO7 SSI0Fss SPRUHE8E – October 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 348 SSI2Clk PM3_GPIO9 MII_TXD1 SSI2Fss PM4_GPIO9 MII_TXD0 PM5_GPIO9 MII_RXDV PM6_GPIO9 MII_RXER PM7_GPIO9 MII_RXCK PN0_GPIO9 I2C0SCL PN1_GPIO9 I2C0SDA PN2_GPIO9 U1Rx PN3_GPIO9 U1Tx General-Purpose Input/Output (GPIO) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 349 PQ0_GPIO1 PQ1_GPIO1 PQ2_GPIO1 U0Rx PQ3_GPIO1 U0Tx PQ4_GPIO1 SSI1Tx PQ5_GPIO1 SSI1Rx PQ6_GPIO1 PQ7_GPIO1 PR0_GPIO1 SSI3Tx PR1_GPIO1 SSI3Rx PR2_GPIO1 SSI3Clk PR3_GPIO1 SSI3Fss SPRUHE8E – October 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 350 15.Alt PR4_GPIO1 PR5_GPIO1 PR6_GPIO1 PR7_GPIO1 PS0_GPIO1 PS1_GPIO1 PS2_GPIO1 PS3_GPIO1 PS4_GPIO1 PS5_GPIO1 PS6_GPIO1 PS7_GPIO1 GPIO Analog I/O 12.Alt 13.Alt 14.Alt 15.Alt General-Purpose Input/Output (GPIO) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 351: Digital I/O Pads
GPIOs are enabled by the GPIODEN register, the M3 can still monitor any GPIO, even if it is mapped to the C28 GPIO mux. SPRUHE8E – October 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 352: Gpiodata Write Example
GPIODATA + 0x0C4 yields as shown in . Figure 4-3. GPIODATA Read Example ADDR[9:2] 0x0C4 GPIODATA Returned V alue General-Purpose Input/Output (GPIO) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 353 The identification registers configured at reset allow software to detect and identify the module as a GPIO block. The identification registers include the GPIOPeriphID0-GPIOPeriphID7 registers as well as the GPIOPCellID0-GPIOPCellID3 registers. SPRUHE8E – October 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 354: Gpio Pad Configuration Examples
Digital Input/Output (SSI) Digital Input/Output (UART) X=Ignored (don't care bit); ?=Can be either 0 or 1, depending on the configuration General-Purpose Input/Output (GPIO) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 355: Gpio Interrupt Configuration Example
GPIO Port J (APB): 0x4003.D000 • GPIO Port J (AHB): 0x4006.0000 • GPIO Port K (AHB): 0x4006.1000 • GPIO Port L (AHB): 0x4006.2000 SPRUHE8E – October 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 356: Gpio Register Map
GPIOPeriphID6 0x0000.0000 GPIO Peripheral Identification 6 0xFDC GPIOPeriphID7 0x0000.0000 GPIO Peripheral Identification 7 0xFE0 GPIOPeriphID0 0x0000.0061 GPIO Peripheral Identification 0 General-Purpose Input/Output (GPIO) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 357: Gpio Data (Gpiodata) Register
Writes to this register only affect bits that are not masked by ADDR[9:2] and are configured as outputs. Section 4.1.3.2.2 for examples of reads and writes. SPRUHE8E – October 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 358: Gpio Direction (Gpiodir) Register
GPIO Interrupt Sense The edge on the corresponding pin is detected (edge-sensitive). The level on the corresponding pin is detected (level-sensitive). General-Purpose Input/Output (GPIO) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 359: Gpio Interrupt Both Edges (Gpioibe) Register
A falling edge or a Low level on the corresponding pin triggers an interrupt. A rising edge or a High level on the corresponding pin triggers an interrupt. SPRUHE8E – October 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 360: Gpio Interrupt Mask (Gpioim) Register
If a bit is clear, either no interrupt has been generated, or the interrupt is masked. General-Purpose Input/Output (GPIO) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 361: Gpio Masked Interrupt Status (Gpiomis) Register
Field Value Description 31-8 Reserved Reserved GPIO Interrupt Raw Status The corresponding interrupt is unaffected. The corresponding interrupt is cleared. SPRUHE8E – October 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 362: Gpio Alternate Function Select (Gpioafsel) Register
The associated pin functions as a GPIO and is controlled by the GPIO registers. The associated pin functions as a peripheral signal and is controlled by the alternate hardware function. General-Purpose Input/Output (GPIO) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 363: Gpio Open Drain Select (Gpioodr) Register
Figure 4-15. GPIO Pull-Up Select (GPIOPUR) Register Reserved Reserved R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUHE8E – October 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 364: Gpio Digital Enable (Gpioden) Register
Pad Weak Pull-Up Enable The digital functions for the corresponding pin are disabled. The digital functions for the corresponding pin are enabled. General-Purpose Input/Output (GPIO) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 365: Gpio Lock (Gpiolock) Register
GPIOCR registers cannot be written with 0x0. These bits are hardwired to 0x1, ensuring that it is always possible to commit new values to the GPIOAFSEL, GPIOPUR, GPIOCSEL, or GPIODEN register bits of these other pins. SPRUHE8E – October 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 366: Gpio Commit (Gpiocr) Register
The analog function of the pin is disabled and the pin is capable of digital functions as specified by the other GPIO configuration registers. The analog function of the pin is enabled. Reserved Reserved General-Purpose Input/Output (GPIO) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 367: Gpio Port Control (Gpiopctl) Register
This field controls the configuration for GPIO pin 1. PMC0 Port Mux Control 0 This field controls the configuration for GPIO pin 0. SPRUHE8E – October 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 368: Gpio Alternate Peripheral Select (Gpioapsel) Register
Alternate peripheral mode disabled Alternate peripheral mode enable APSEL0 Alternate peripheral select 0 Alternate peripheral mode disabled Alternate peripheral mode enable General-Purpose Input/Output (GPIO) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 369: Gpio Core Select (Gpiocsel) Register
Selects M3 GPIO mux Selects C28 GPIO mux CSEL0 Core select 0 Selects M3 GPIO mux Selects C28 GPIO mux SPRUHE8E – October 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 370: Gpio Peripheral Identification 4 (Gpioperiphid4) Register
Table 4-24. GPIO Peripheral Identification 4 (GPIOPeriphID4) Register Field Descriptions Field Value Description 31-8 Reserved Reserved PID4 GPIO Peripheral ID Register [7:0] General-Purpose Input/Output (GPIO) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 371: Gpio Peripheral Identification 5 (Gpioperiphid5) Register
Table 4-25. GPIO Peripheral Identification 5 (GPIOPeriphID5) Register Field Descriptions Field Value Description 31-8 Reserved Reserved PID5 GPIO Peripheral ID Register [15:8] SPRUHE8E – October 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 372: Gpio Peripheral Identification 6 (Gpioperiphid6) Register
Table 4-26. GPIO Peripheral Identification 6 (GPIOPeriphID6) Register Field Descriptions Field Value Description 31-8 Reserved Reserved PID6 GPIO Peripheral ID Register [23:16] General-Purpose Input/Output (GPIO) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 373: Gpio Peripheral Identification 7 (Gpioperiphid7) Register
Table 4-27. GPIO Peripheral Identification 7 (GPIOPeriphID7) Register Field Descriptions Field Value Description 31-8 Reserved Reserved PID7 GPIO Peripheral ID Register [31:24] SPRUHE8E – October 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 374: Gpio Peripheral Identification 0 (Gpioperiphid0) Register
Reserved Reserved PID1 GPIO Peripheral ID Register [15:8] Can be used by software to identify the presence of this peripheral. General-Purpose Input/Output (GPIO) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 375: Gpio Peripheral Identification 2 (Gpioperiphid2) Register
32-bit register. The register is used as a standard cross- peripheral identification system. SPRUHE8E – October 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 376: Gpio Primecell Identification 0 (Gpiopcellid0) Register
Figure 4-33. GPIO PrimeCell Identification 2 (GPIOPCellID2) Register Reserved Reserved CID2 R-0x5h LEGEND: R/W = Read/Write; R = Read only; -n = value after reset General-Purpose Input/Output (GPIO) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 377: Gpio Primecell Identification 3 (Gpiopcellid3) Register
Table 4-35. GPIO PrimeCell Identification 3 (GPIOPCellID3) Register Register Field Descriptions Field Value Description 31-8 Reserved Reserved CID3 GPIO PrimeCell ID Register [31:24]. Provides software a standard cross-peripheral identification system. SPRUHE8E – October 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 378 Analog Port 2 consists of AIO16-AIO31 Figure 4-35 through Figure 4-38 shows the basic modes of operation for the GPIO module. General-Purpose Input/Output (GPIO) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 379: Gpio0 To Gpio31 Multiplexing Diagram
GPIOs. If the GPIO is set as an M3 GPIO, the C28 GPIO MUX inputs are still active and can be read. SPRUHE8E – October 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 380: Gpio32, Gpio33 Multiplexing Diagram
The input qualification circuit is not reset when modes are changed (such as changing from output to input mode). Any state will get flushed by the circuit eventually. General-Purpose Input/Output (GPIO) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 381: Gpio34, Gpio199 Multiplexing Diagram
GPIOs. If the GPIO is set as an M3 GPIO, the C28 GPIO MUX inputs are still active and can be read. • The input qualification circuit is not reset when modes are changed (such as changing from output to SPRUHE8E – October 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 382: Analog/Gpio Multiplexing
SYNC (Read) AIODAT Reg (Latch) AIOMUX1 Reg AIOSET, AIOCLEAR, AIOTOGGLE Regs AIODIR Reg (Latch) (0 = Input, 1 = Output) General-Purpose Input/Output (GPIO) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 383: Gpio Mux-To-Trip Input Connectivity
Refer to the GPIO chapter for more information. The GPTRIPxSEL register must also be used to allow ECAP modules to capture data on a pin. Refer to the ECAP chapter for more information. SPRUHE8E – October 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 384: Gpio Control Registers
GPIO G Direction Register (GPIO192 - GPIO199) An X in a table cell indicates the bit can be 0 or 1. General-Purpose Input/Output (GPIO) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 385: Gpio Trip Input Select Registers
(GPIOPUR) register. This register is located in the M3 GPIO register space. All GPIO-capable pins have the pullup disabled by default. The AIOx pins do not have internal pull-up resistors. 4. Select input qualification: SPRUHE8E – October 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 386 NOTE: There is a 2-SYSCLKOUT cycle delay from when a write to configuration registers such as GPxMUXn and GPxQSELn occurs to when the action is valid General-Purpose Input/Output (GPIO) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 387: Gpio Data Registers
(GPIO192 - GPIO199) GPGTOGGLE 0x6FC6 GPIO G Toggle Register (GPIO192 - GPIO199) AIODAT 0x6FD8 Analog IO Data Register (AIO0 - AIO31) SPRUHE8E – October 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 388 • GPxCLEAR/AIOCLEAR Registers The clear registers are used to drive specified GPIO pins low without disturbing other pins. Each I/O General-Purpose Input/Output (GPIO) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 389 1) the sampling period, or how often the signal is sampled, and 2) the number of samples to be taken. SPRUHE8E – October 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 390: Input Qualification Using A Sampling Window
If, for example, f = 150 MHz SYSCLKOUT then the signal will be sampled at 150 MHz or one sample every 6.67 ns. General-Purpose Input/Output (GPIO) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 391: Case 1: Three-Sample Sampling Window Width
(SP) = 2 × GPxCTRL[QUALPRDn] × T SYSCLKOUT This configuration results in the following: • The width of the sampling window is: . SPRUHE8E – October 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 392: Input Qualifier Clock Cycles
(5 x QUALPRD x 2) SYSCLKOUT cycles. That would ensure 5 sampling periods for detection to occur. Since external signals are driven asynchronously, an 13-SYSCLKOUT-wide pulse ensures reliable recognition. General-Purpose Input/Output (GPIO) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 393: Gpio And Peripheral Multiplexing (Mux)
Table 4-43 and the input would not be connected to GPIO5 or GPIO24. SPRUHE8E – October 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 394: Default State Of Peripheral Input
This value will be assigned to the peripheral input if more then one pin has been assigned to the peripheral function in the GPxMUX1/2 registers or if no pin has been assigned. General-Purpose Input/Output (GPIO) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 395: Gpioa Mux
This selection is a reserved configuration for future expansion. SPRUHE8E – October 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 396: Gpiob Mux
Reserved EPWM8A (O) 27-26 GPIO61 Reserved Reserved EPWM8B (O) 29-28 GPIO62 Reserved Reserved EPWM9A(O) 31-30 GPIO63/XCLKIN Reserved Reserved EPWM9B (O) General-Purpose Input/Output (GPIO) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 397: C28 Gpioc Mux
25-24 PM4_GPIO92 Reserved MDXA Reserved 27-26 PM5_GPIO93 Reserved MDRA Reserved 29-28 PM6_GPIO94 Reserved MCLKXA Reserved 31-30 PM7_GPIO95 Reserved MFSXA Reserved SPRUHE8E – October 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 398: C28 Gpiod Mux
25-24 PR4_GPIO124 EPWM7A Reserved Reserved 27-26 PR5_GPIO125 EPWM7B Reserved Reserved 29-28 PR6_GPIO126 EPWM8A Reserved Reserved 31-30 PR7_GPIO127 EPWM8B Reserved Reserved General-Purpose Input/Output (GPIO) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 399: C28 Gpioe Mux
Reserved PS1_GPIO132 EPWM11A Reserved Reserved 11-10 PS1_GPIO133 EPWM11B Reserved Reserved 13-12 PS1_GPIO134 EPWM12A Reserved Reserved 15-14 PS7_GPIO135 EPWM12B Reserved Reserved SPRUHE8E – October 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 400: Gpiog Mux
ADCINB2 (I), COMP4B (I) 23-22 ADCINB3 (I) ADCINB3 (I) 25-24 AIO28 (I/O) ADCINB4 (I), COMP5B (I) 27-26 ADCINB5 (I) ADCINB5 (I) General-Purpose Input/Output (GPIO) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 401 ADCINB6 (I), COMP6B (1) 31-30 ADCINB7 (I) ADCINB7 (I) Note: AIOMUX1 registers correspond to ADC1 and AIOMUX2 registers correspond to ADC2. SPRUHE8E – October 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 402: Register Bit Definitions
EPWM6A - ePWM6 output A (O) Reserved ADCSOCBO - ADC Start of conversion B (O) This register is EALLOW protected. General-Purpose Input/Output (GPIO) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 403 Configure the GPIO1 pin as: GPIO1 - General purpose I/O 1 (default) (I/O) EPWM1B - ePWM1 output B (O) ECAP - eCAP6 (I/O) Reserved SPRUHE8E – October 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 404: Gpio Port A Mux 2 (Gpamux2) Register
If reserved configurations are selected, then the state of the pin will be undefined and the pin may be driven. These selections are reserved for future expansion and should not be used. General-Purpose Input/Output (GPIO) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 405 Configure the GPIO18 pin as: GPIO18 - General purpose I/O 18 (default) (I/O) SPICLKA - SPI-A clock (I/O) Reserved Reserved SPRUHE8E – October 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 406: Gpio Port B Mux 1 (Gpbmux1) Register
Reserved Reserved Reserved 25:24 GPIO44 Configure this pin as: GPIO 44 - general purpose I/O 44 (default) Reserved Reserved Reserved General-Purpose Input/Output (GPIO) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 407 Configure this pin as: GPIO 35 - general purpose I/O 35 (default) SCITXDA - SCI - A transmit data (O) Reserved Reserved SPRUHE8E – October 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 408: Gpio Port B Mux 2 (Gpbmux2) Register
Configure this pin as: GPIO 61 - general purpose I/O 61 (default) Reserved Reserved EPWM8B - ePWM8 output B (O) General-Purpose Input/Output (GPIO) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 409 GPIO52 Configure this pin as: GPIO 52 - general purpose I/O 52 (default) EQEP1S - eQEP1 strobe (I/O) Reserved Reserved SPRUHE8E – October 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 410: Gpio Port C Mux 1 (Gpcmux1) Register
Value Description 31-30 GPIO79 Configure this pin as: GPIO 79 - general purpose I/O 79 GPIO (default) Reserved Reserved Reserved General-Purpose Input/Output (GPIO) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 411 Reserved Reserved Reserved 13-12 GPIO70 Configure this pin as: GPIO 70 - general purpose I/O 70 (default) Reserved Reserved Reserved SPRUHE8E – October 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 412 GPIO Port C MUX 2 (GPCMUX2) Register The GPIO Port C MUX 2 (GPCMUX2) register is shown and described in the figure and table below. General-Purpose Input/Output (GPIO) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 413: Gpio Port C Mux 2 (Gpcmux2) Register
Reserved Reserved 21-20 GPIO90 Configure this pin as: GPIO 90 - general purpose I/O 90 GPIO (default) Reserved Reserved Reserved SPRUHE8E – October 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 414 GPIO 82 - general purpose I/O 82 (default) Reserved Reserved Reserved GPIO81 Configure this pin as: GPIO 81 - general purpose I/O 81 (default) Reserved Reserved Reserved General-Purpose Input/Output (GPIO) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 415: Gpio Port D Mux 1 (Gpdmux1) Register
Reserved Reserved 25-24 GPIO108 Configure this pin as: GPIO 108 - general purpose I/O 108 GPIO (default) EQEP1S Reserved Reserved SPRUHE8E – October 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 416 Reserved Reserved Reserved GPIO99 Configure this pin as: GPIO 99 - general purpose I/O 99 GPIO (default) Reserved Reserved Reserved General-Purpose Input/Output (GPIO) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 417: Gpio Port D Mux 2 (Gpdmux2) Register
Reserved Reserved 29-28 GPIO126 Configure this pin as: GPIO 126 - general purpose I/O 126 GPIO (default) EPWM8A Reserved Reserved SPRUHE8E – October 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 418 SCITXDA Reserved 11-10 GPIO117 Configure this pin as: GPIO 117 - general purpose I/O 117 GPIO (default) Reserved Reserved Reserved General-Purpose Input/Output (GPIO) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 419: Gpio Port E Mux 1 (Gpemux1) Register
Reserved Reserved 15-14 GPIO135 Configure this pin as: GPIO 135 - general purpose I/O 135 GPIO (default) EPWM12B Reserved Reserved SPRUHE8E – October 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 420: Gpio Port G Mux 1 (Gpgmux1) Register
R/W-0 R/W-0 R/W-0 R/W0 R/W0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset General-Purpose Input/Output (GPIO) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 421: Gpio Port G Mux 1 (Gpgmux1) Register Field Descriptions
4.2.7.11 Analog I/O MUX 1 (AIOMUX1) Register The Analog I/O MUX 1 (AIOMUX1) register is shown and described in the figure and table below. SPRUHE8E – October 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 422: Analog I/O Mux 1 (Aiomux1) Register
R/W-0x2 R/W-0x2 R/W-0x2 R/W-0x2 R/W-0x2 R/W-0x2 R/W-0xA LEGEND: R/W = Read/Write; R = Read only; -n = value after reset General-Purpose Input/Output (GPIO) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 423: Analog I/O Mux 2 (Aiomux2) Register Field Descriptions
AIO18 enabled 10 or 11 AIO18 disabled (default) Reserved Any writes to these bit(s) must always have a value of 2. SPRUHE8E – October 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 424: Gpio Port A Qualification Control (Gpactrl) Register
. . . 0xFF Sampling Period = 510 × T SYSCLKOUT This register is EALLOW protected. indicates the period of SYSCLKOUT. SYSCLKOUT General-Purpose Input/Output (GPIO) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 425: Gpio Port B Qualification Control (Gpbctrl) Register
4.2.7.15 GPIO Port C Qualification Control (GPCCTRL) Register The GPIO Port C Qualification Control (GPCCTRL) register is shown and described in the figure and table below. SPRUHE8E – October 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 426: Gpio Port C Qualification Control (Gpcctrl) Register
Figure 4-57. GPIO Port C Qualification Control (GPDCTRL) Register QUALPRD3 QUALPRD1 R/W-0 QUALPRD1 QUALPRD0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset General-Purpose Input/Output (GPIO) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 427: Gpio Port E Qualification Control (Gpectrl) Register
0x00 QUALPRD = SYSCLKOUT 0x01 QUALPRD = SYSCLKOUT/2 0x02 QUALPRD = SYSCLKOUT/4 ..0xFF QUALPRD = SYSCLKOUT/510 SPRUHE8E – October 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 428: Gpio Port G Qualification Control (Gpgctrl) Register
Note: GPIO on Port E is synchronized to the analog subsystem clock by default. indicates the period of SYSCLKOUT. SYSCLKOUT General-Purpose Input/Output (GPIO) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 429: Gpio Port A Qualification Select 1 (Gpaqsel1) Register
If the pin is configured as a GPIO input, then this option is the same as 0,0 or synchronize to SYSCLKOUT. This register is EALLOW protected. SPRUHE8E – October 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 430: Gpio Port B Qualification Select 1 (Gpbqsel1) Register
If the pin is configured as a GPIO input, then this option is the same as 0,0 or synchronize to SYSCLKOUT. This register is EALLOW protected. General-Purpose Input/Output (GPIO) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 431: Gpio Port C Qualification Select 1 (Gpcqsel1) Register
19-18 GPIO73 Select input qualification type for GPIO73 Sync Qualification (3 samples) Qualification (6 samples) Async (no Sync or Qualification) SPRUHE8E – October 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 432 Async (no Sync or Qualification) GPIO64 Select input qualification type for GPIO64: Sync Qualification (3 samples) Qualification (6 samples) Async (no Sync or Qualification) General-Purpose Input/Output (GPIO) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 433: Gpio Port C Qualification Select 2 (Gpcqsel2) Register
19-18 GPIO89 Select input qualification type for GPIO89 Sync Qualification (3 samples) Qualification (6 samples) Async (no Sync or Qualification) SPRUHE8E – October 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 434 Async (no Sync or Qualification) GPIO80 Select input qualification type for GPIO80 Sync Qualification (3 samples) Qualification (6 samples) Async (no Sync or Qualification) General-Purpose Input/Output (GPIO) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 435: Gpio Port D Qualification Select 1 (Gpedsel1) Register
19-18 GPIO105 Select input qualification type for GPIO105 Sync Qualification (3 samples) Qualification (6 samples) Async (no Sync or Qualification) SPRUHE8E – October 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 436 Async (no Sync or Qualification) GPIO96 Select input qualification type for GPIO96 Sync Qualification (3 samples) Qualification (6 samples) Async (no Sync or Qualification) General-Purpose Input/Output (GPIO) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 437: Gpio Port D Qualification Select 2 (Gpdqsel2) Register
19-18 GPIO121 Select input qualification type for GPIO121 Sync Qualification (3 samples) Qualification (6 samples) Async (no Sync or Qualification) SPRUHE8E – October 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 438 Async (no Sync or Qualification) GPIO112 Select input qualification type for GPIO112 Sync Qualification (3 samples) Qualification (6 samples) Async (no Sync or Qualification) General-Purpose Input/Output (GPIO) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 439: Gpio Port E Qualification Select 1 (Gpeqsel1) Register
Async (no Sync or Qualification) GPIO130 Select input qualification type for GPIO130 Sync Qualification (3 samples) Qualification (6 samples) Async (no Sync or Qualification) SPRUHE8E – October 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 440: Gpio Port G Qualification Select 1 (Gpgqsel1) Register
If the pin is configured as a GPIO input, then this option is the same as 0,0 or synchronize to SYSCLKOUT. This register is EALLOW protected. General-Purpose Input/Output (GPIO) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 441: Gpio Port E Qualification Select 1 (Gpeqsel1) Register
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUHE8E – October 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 442: Gpio Port B Direction (Gpbdir) Register
4.2.7.32 GPIO Port C Direction (GPCDIR) Register The GPIO Port C Direction (GPCDIR) Register is shown and described in the figure and table below. General-Purpose Input/Output (GPIO) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 443: Gpio Port C Direction (Gpcdir) Register
Configures the GPIO pin as an input. (default) Configures the GPIO pin as an output This register is EALLOW protected. SPRUHE8E – October 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 444: Gpio Port G Direction (Gpedir) Register
4.2.7.36 GPIO Port G Pullup Disable (GPGPUD) Register The GPIO Port G Pullup Disable (GPGPUD) register is shown and described in the figure and table below. General-Purpose Input/Output (GPIO) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 445: Gpio Port G Pullup Disable (Gpgpud)
Configures the AIO pin as an input. (default) Configures the AIO pin as an output SPRUHE8E – October 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 446: Gpio Port A Data (Gpadat) Register
Writing a 1will force an output of 1if the pin is configured as a GPIO output in the appropriate GPAMUX1/2 and GPADIR registers; otherwise, the value is latched but not used to drive the pin. General-Purpose Input/Output (GPIO) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 447: Gpio Port B Data (Gpbdat) Register
Writing a 1 will force an output of 1 if the pin is configured as a GPIO output in the GPBMUX1 and GPBDIR registers; otherwise, the value is latched but not used to drive the pin. SPRUHE8E – October 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 448: Gpio Port C Data (Gpcdat) Register
Writing a 1 will force an output of 1 if the pin is configured as a GPIO output in the GPCMUX1 and GPCDIR registers; otherwise, the value is latched but not used to drive the pin. General-Purpose Input/Output (GPIO) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 449: Gpio Port D Data (Gpddat) Register
Writing a 1 will force an output of 1 if the pin is configured as a GPIO output in the GPDMUX1 and GPDDIR registers; otherwise, the value is latched but not used to drive the pin. SPRUHE8E – October 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 450: Gpio Port E Data (Gpedat) Register
Writing a 1 will force an output of 1 if the pin is configured as a GPIO output in the GPEMUX1 and GPEDIR registers; otherwise, the value is latched but not used to drive the pin. General-Purpose Input/Output (GPIO) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 451: Gpio Port G Data (Gpgdat) Register
Writing a 1 will force an output of 1 if the pin is configured as a GPIO output in the GPGMUX1 and GPGDIR registers; otherwise, the value is latched but not used to drive the pin. SPRUHE8E – October 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 452: Analog I/O Dat (Aiodat) Register
Writing a 1will force an output of 1if the pin is configured as a AIO output in the appropriate registers; otherwise, the value is latched but not used to drive the pin. General-Purpose Input/Output (GPIO) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 453: Gpio Port A Set, Clear And Toggle (Gpaset, Gpaclear, Gpatoggle) Registers
GPIO output then it will be driven in the opposite direction of its current state. If the pin is not configured as a GPIO output then the latch is toggled but the pin is not driven. SPRUHE8E – October 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 454: Gpio Port B Set, Clear And Toggle (Gpbset, Gpbclear, Gpbtoggle) Registers
GPIO output then the latch is cleared but the pin is not driven. General-Purpose Input/Output (GPIO) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 455: Gpio Port C Set, Clear And Toggle (Gpcset, Gpcclear, Gpctoggle) Registers
GPIO output then the latch is cleared but the pin is not driven. SPRUHE8E – October 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 456: Gpio Port D Set, Clear And Toggle (Gpdset, Gpdclear, Gpdtoggle) Registers
GPIO output then the latch is cleared but the pin is not driven. General-Purpose Input/Output (GPIO) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 457: Gpio Port E Set, Clear And Toggle (Gpeset, Gpeclear, Gpetoggle) Registers
GPIO output then the latch is cleared but the pin is not driven. SPRUHE8E – October 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 458: Gpio Port G Set, Clear And Toggle (Gpgset, Gpgclear, Gpgtoggle) Registers
GPIO output then the latch is cleared but the pin is not driven. General-Purpose Input/Output (GPIO) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 459: Analog I/O Toggle (Aioset, Aioclear, Aiotoggle) Register
AIO output then the latch is cleared but the pin is not driven. SPRUHE8E – October 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 460: Gpio Trip Input Select Register (Gptripxsel)
The GPIO Low Power Mode Wakeup Select 1 (GPIOLPMSEL1) register is shown and described in the figure and table below. General-Purpose Input/Output (GPIO) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 461: Gpio Low Power Mode Wakeup Select 1 (Gpiolpmsel1) Register
If the respective bit is set to 1, the signal on the corresponding pin is able to wake the device from both HALT and STANDBY low power modes. This register is EALLOW protected. SPRUHE8E – October 2012 – Revised November 2019 General-Purpose Input/Output (GPIO) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 462: Internal Memory
This chapter provides information on the RAM and flash memory modules..........................Topic Page ..................RAM Control Module ................RAM Control Module Registers ................ Flash Controller Memory Module ....................Flash Registers Internal Memory SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 463: Ram Control Module
M3 subsystem are mapped to the M3 CPU and M3 µDMA. Similarly for the C28x subsystem, these RAM blocks are mapped to the C28 CPU and C28 DMA. SPRUHE8E – October 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 464: Shared Ram (Dedicated To Subsystem)
MSxSRCR register (when the RAM block is owned by the M3 subsystem) or the CSxSRCR register (when the RAM block is owned by the C28x subsystem). Internal Memory SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 465: Simple Round Robin
Access Table 5-3. Extra Wait State Cycle Accesses Access Granted Cycle #1 Master1 Access Master1 Access Cycle #2 Master2 Access Idle SPRUHE8E – October 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 466: Round-Robin Exception
Max cycle latency for an access to Sx memory from any master is five cycles when M3 is master for that Sx memory. The following are the possible accesses with details of how many cycles each access Internal Memory SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 467 Non-master CPU write protection violation (only applicable to Sx memories) If a write access is made to Sx memory by the non-master CPU, it’s called a non-master write protection violation. SPRUHE8E – October 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 469 These need to be handled appropriately in software using the status and interrupt indications provided. SPRUHE8E – October 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 470: Error Handling In Different Scenarios
The following table shows the bit mapping for the ECC/parity bits when they are read in RAMTEST mode using their respective addresses. Internal Memory SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 471: Mapping Of Ecc Bits In Read Data From Ecc/Parity Address Map
In case of Sx memory, the CPU of the subsystem, which is configured as the master for the particular Sx RAM block, can only initiate the RAM initialization. SPRUHE8E – October 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 472: Ram Control Module Registers
M3 µDMA Corrected Read Error Address Register MUEFLG 0x20 M3 Uncorrectable Error Flag Register MUEFRC 0x24 M3 Uncorrectable Error Force Register Internal Memory SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 473: C28X Ram Configuration Registers Summary
M0, M1 and C28T0M3_MSG_RAM INIT Done Register CLxRINITDONE1 0x32 C28x C28x Lx RAM_INIT_DONE Register 1 CSxRINITDONE1 0x36 C28x C28x Sx RAM_INIT_DONE Register 1 SPRUHE8E – October 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 474: C28X Ram Error Registers Summary
Register CMDMAWRAVADDR 0x3A C28x Master DMA Write Access Violation Address Register CMFAVADDR 0x3C C28x Master CPU Fetch Access Violation Address Register Internal Memory SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 475: M3 Ram Configuration Registers
CPU Fetch Protection C0 M3 CPU Fetch allowed from C0 RAM block. M3 CPU Fetch not allowed from C0 RAM block. SPRUHE8E – October 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 476: Cx Shram Configuration Register 1 (Cxsrcr1)
M3 CPU Fetch not allowed from C3 RAM Block. Reserved Reserved CPUWRPROTC2 M3 CPU Write allowed to C2 RAM Block. M3 CPU Write not allowed to C2 RAM Block Internal Memory SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 477: Cx Shram Configuration Register 2 (Cxsrcr2)
15-11 Reserved Reserved CPUWRPROTC7 M3 CPU Write allowed to C7 RAM Block. M3 CPU Write not allowed to C7 RAM Block. SPRUHE8E – October 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 478: Cx Shram Configuration Register 3 (Cxsrcr3)
23-19 Reserved Reserved CPUWRPROTC12 M3 CPU Write allowed to C12 RAM Block. M3 CPU Write not allowed to C12 RAM Block. Internal Memory SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 479: Cx Shram Configuration Register 4 (Cxsrcr4)
31-11 Reserved Reserved CPUWRPROTC15 M3 CPU Write allowed to C15 RAM Block. M3 CPU Write not allowed to C15 RAM Block. SPRUHE8E – October 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 480 M3 uDMA Write not allowed to C14 RAM Block. FETCHPROTC14 M3 CPU Fetch allowed from C14 RAM Block. M3 CPU Fetch not allowed from C14 RAM Block. Internal Memory SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 481: Sx Shram Master Select Register (Msxmsel)
C28 subsystem is master for S1 RAM block. C28 CPU/DMA accesses are allowed based on the setting of protection bits in the CSxSRCR register. SPRUHE8E – October 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 482: M3 Sx Shram Configuration Register 1 (Msxsrcr1)
µDMA Write Protection S2 M3 µDMA write allowed to S2 RAM block. M3 µDMA write not allowed to S2 RAM block. Internal Memory SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 483 CPU Fetch Protection S0 M3 CPU Fetch allowed from S0 RAM block. M3 CPU Fetch not allowed from S0 RAM block. SPRUHE8E – October 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 484: M3 Sx Shram Configuration Register 2 (Msxsrcr2)
µDMA Write Protection S5 M3 µDMA write allowed to S5 RAM block. M3 µDMA write not allowed to S5 RAM block. Internal Memory SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 485 CPU Fetch Protection S4 M3 CPU Fetch allowed from S4 RAM block. M3 CPU Fetch not allowed from S4 RAM block. SPRUHE8E – October 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 486: M3Toc28_Msg_Ram Configuration Register (Mtocmsgrcr)
Reserved Reserved DMAWRPROT µDMA Write Protection M3 µDMA write allowed to MTOC_MSG_RAM. M3 µDMA write not allowed to MTOC_MSG_RAM. Reserved Reserved Internal Memory SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 487: Cx Ram Test And Initialization Register 1 (Cxrtestinit1)
No action taken. Initialize all address locations of C0 RAM block with data 0x0 and corresponding data an address ECC/parity bits. SPRUHE8E – October 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 488: M3 Sx Ram Test And Initialization Register 1 (Msxrtestinit1)
Initialize all address locations of S4 RAM block with data 0x0 and corresponding data an address ECC/parity bits. Applicabale only if M3 subsystem is master for S4 memory. Internal Memory SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 489 Initialize all address locations of S0 RAM block with data 0x0 and corresponding data an address ECC/parity bits. Applicabale only if M3 subsystem is master for S0 memory. SPRUHE8E – October 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 490: Mtoc_Msg_Ram Test And Initialization Register (Mtocrtestinit)
MTOCMSGRAM No action taken. Initialize all address locations of MTOC_MSG_RAM block with data 0x0 and corresponding data and address ECC/parity bits. Internal Memory SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 491: Cx Ram Initdone Register 1 (Cxrinitdone1)
RAM initialization is done for C0 RAM block. C0 RAM can be accessed by M3 CPU. This status bit gets cleared when the RAMINIT bit is set for C0 RAM block. SPRUHE8E – October 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 492: M3 Sx Ram Initdone Register 1 (Msxrinitdone1)
RAM initialization is done for S3 RAM block. S3 RAM can be accessed by M3 CPU/µDMA or C28x CPU/DMA. This status bit gets cleared when the RAMINIT bit is set for S3 RAM block. Reserved Reserved Internal Memory SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 493 RAM initialization is done for S0 RAM block. S0 RAM can be accessed by M3 CPU/µDMA or C28x CPU/DMA. This status bit gets cleared when the RAMINIT bit is set for S0 RAM block. SPRUHE8E – October 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 494: M3 Ram Error Registers
This register contains the address where uncorrectable error occurs during M3 µDMA byte writes. Only the address coresponding to the last error is stored. Internal Memory SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 495: M3 Cpu Uncorrectable Read Error Address Register (Mcuncreaddr)
This register contains the address where uncorrectable error occurs during M3 µDMA data read. Only the address coresponding to the last error is stored. SPRUHE8E – October 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 496: M3 Cpu Corrected Read Error Address Register (Mcpucreaddr)
This register contains the address where correctable error occurs during M3 µDMA data read. Only the address coresponding to the last error is stored. Internal Memory SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 497: M3 Uncorrectable Error Flag Register (Mueflg)
M3 CPU uncorrectable write error occurred. Once this bit is set, it can be cleared by setting the corresponding error clear bit in the MUECLR register. SPRUHE8E – October 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 498: M3 Uncorrectable Error Force Register (Muefrc)
M3 CPU Uncorrectable Write Error Force. Any reads to this bit will return a 0. Setting this bit to 1 will set the M3 CPU uncorrectable write error flag status. Internal Memory SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 499: M3 Uncorrectable Error Flag Clear Register (Mueclr)
MCEIE register. Note: Writing a value equal to the MCETRES generates an interrupt and sets the MCEFLG. SPRUHE8E – October 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 500: M3 Corrected Error Threshold Register (Mcetres)
M3 Correctable Error Flag Force. Any read to this bit returns a 0. Setting this bit to 1 sets the MCEFLG flag in the MCEFLG register. Internal Memory SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 501: M3 Corrected Error Threshold Exceeded Flag Clear Register (Mceclr)
Correctable error interrupt is not generated even though the MCEFLG flag is set. Correctable error interrupt is generated when the MCEFLG flag is set. SPRUHE8E – October 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 502: Non-Master Access Violation Flag Register (Mnmavflg)
31-3 Reserved Reserved CPUWRITE Non-Master CPU Write Access Violation Clear No effect. Clears the corresponding non-master DMA write access violation flag. Internal Memory SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 503: Master Access Violation Flag Register (Mmavflg)
Block for which FETCHPROT is set to 1. Once this bit is set, it can be cleared by setting the corresponding error clear bit in the MNMAVCLR register. SPRUHE8E – October 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 504: Master Access Violation Flag Clear Register (Mmavclr)
Non-Master CPU Write Access Violation Address This holds the address at which M3 CPU attempted a write access and the non-master CPU write access violation occurred. Internal Memory SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 505: Non-Master Dma Write Access Violation Address Register (Mnmdmawravaddr)
Master CPU Write Access Violation Address This holds the address at which M3 CPU attempted a write access and the master CPU write access violation occurred. SPRUHE8E – October 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 506: Master Dma Write Access Violation Address Register (Mmdmawravaddr)
Master CPU Fetch Access Violation Address This holds the address at which M3 CPU attempted a code fetch and the master CPU fetch access violation occurred. Internal Memory SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 507: C28X Ram Configuration Registers
CPU Fetch Protection L0 C28x CPU Fetch allowed from L0 RAM block. C28x CPU Fetch not allowed from L0 RAM block. SPRUHE8E – October 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 508: Lx Shram Configuration Register 1 (Lxsrcr1)
CPU Fetch Protection L2 C28x CPU Fetch allowed from L2 RAM block. C28x CPU Fetch not allowed from L2 RAM block. Internal Memory SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 509: C28X Sx Shram Master Select Register (Csxmsel)
C28 subsystem is master for S1 RAM block. C28 CPU/DMA accesses are allowed based on the setting of protection bits in the CSxSRCR register. SPRUHE8E – October 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 510: C28X Sx Shram Configuration Register 1 (Csxsrcr1)
DMA Write Protection S2 C28x DMA write allowed to S2 RAM block. C28x DMA write not allowed to S2 RAM block. Internal Memory SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 511: C28X Sx Shram Configuration Register 2 (Csxsrcr2)
R/W-0 Reserved CPUWRPROT DMAWRPROT FETCHPROTS R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUHE8E – October 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 512: C28X Sx Shram Configuration Register 2 (Csxsrcr2) Field Descriptions
CPU Fetch Protection S4 C28x CPU Fetch allowed from S4 RAM block. C28x CPU Fetch not allowed from S4 RAM block. Internal Memory SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 513: C28Toc28_Msg_Ram Configuration Register (Ctommsgrcr)
Reserved Reserved DMAWRPROT DMA Write Protection C28x DMA write allowed to CTOM_MSG_RAM. C28x DMA write not allowed to CTOM_MSG_RAM. Reserved Reserved SPRUHE8E – October 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 514: M0, M1 And C28T0C28_Msg_Ram Test And Initialization Register (C28Rtestinit)
No action taken. Initialize all address locations of M0 RAM block with data 0x0 and corresponding data an address ECC/parity bits. Internal Memory SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 515: Lx Ram Test And Initialization Register 1 (Clxrtestinit1)
No action taken. Initialize all address locations of L0 RAM block with data 0x0 and corresponding data an address ECC/parity bits. SPRUHE8E – October 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 516: C28X Sx Ram Test And Initialization Register 1 (Csxrtestinit1)
RAMTEST feature is disabled for S4 RAM block. RAMTEST feature is enabled for S4 RAM block. ECC/parity logic is bypassed for memory accesses. Internal Memory SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 517 Initialize all address locations of S0 RAM block with data 0x0 and corresponding data an address ECC/parity bits. Applicable only if C28x subsystem is master for S0 memory. SPRUHE8E – October 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 518: M0, M1 And C28T0M3_Msg_Ram Init Done Register (C28Rinitdone)
RAM initialization is done for M0 RAM block. M0 RAM can be accessed by M3 CPU. This status bit gets cleared when the RAMINIT bit is set for M0 RAM block. Internal Memory SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 519: C28X Lx Ram_Init_Done Register 1 (Clxrinitdone1)
RAM initialization is done for C0 RAM block. C0 RAM can be accessed by M3 CPU. This status bit gets cleared when the RAMINIT bit is set for C0 RAM block. SPRUHE8E – October 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 520: C28X Sx Ram_Init_Done Register 1 (Csxrinitdone1)
RAM initialization is done for S3 RAM block. S3 RAM can be accessed by M3 CPU/µDMA or C28x CPU/DMA. This status bit gets cleared when the RAMINIT bit is set for S3 RAM block. Reserved Reserved Internal Memory SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 521 RAM initialization is done for S0 RAM block. S0 RAM can be accessed by M3 CPU/µDMA or C28x CPU/DMA. This status bit gets cleared when the RAMINIT bit is set for S0 RAM block. SPRUHE8E – October 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 522: C28X Ram Error Registers
This register contains the address where correctable error occurs during C28x CPU data read or fetch. Only the address coresponding to the last error is stored. Internal Memory SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 523: C28X Dma Corrected Read Error Address Register (Cdmacreaddr)
C28x CPU uncorrectable read error occurred. Once this bit is set, it can be cleared by setting the corresponding error clear bit in the CUECLR register. SPRUHE8E – October 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 524: C28X Uncorrectable Error Force Register (Cuefrc)
C28x CPU Uncorrectable Read Error Clear. Any reads to this bit will return a 0. No effect Clears the C28x CPU uncorrectable read error flag. Internal Memory SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 525: C28X Corrected Error Counter Register (Ccecntr)
C28x CPU/DMA Corrected Error Threshold Value If CCECNTR = CCETRES, correctable error interrupt gets generated if it is enabled in the CCEIE register. SPRUHE8E – October 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 526: C28X Corrected Error Threshold Exceeded Flag Register (Cceflg)
C28x Correctable Error Flag Force. Any reads to this bit will return a 0. Setting this bit to 1 sets the CCEFLG flag in the CCEFLG register. Internal Memory SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 527: C28X Corrected Error Threshold Exceeded Flag Clear Register (Cceclr)
Correctable error interrupt is not generated even though the CCEFLG flag is set. Correctable error interrupt is generated when the CCEFLG flag is set. SPRUHE8E – October 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 528: Non-Master Access Violation Flag Register (Cnmavflg)
RAM block for which M3 subsystem is the master. Once this bit is set, it can be cleared by setting the corresponding error clear bit in the CNMAVCLR register. Internal Memory SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 529: Non-Master Access Violation Force Register (Cnmavfrc)
Non-Master CPU Fetch Access Violation Clear. Any reads to this bit will return a 0. No effect. Clears the corresponding non-master CPU fetch access violation flag. SPRUHE8E – October 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 530: Master Access Violation Flag Register (Cmavflg)
Master CPU Write Access Violation Force. Any reads to this bit will return a 0. No effect. Sets the CPUFETCH flag in the CNMAVFLG register. Internal Memory SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 531 Master CPU Fetch Access Violation Force. Any reads to this bit will return a 0. No effect. Sets the CPUFETCH flag in the CNMAVFLG register. SPRUHE8E – October 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 532: Master Access Violation Flag Clear Register (Cmavclr)
Master CPU Fetch Access Violation Clear. Any reads to this bit will return a 0. No effect. Clears the corresponding master CPU fetch access violation flag. Internal Memory SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 533: Non-Master Cpu Write Access Violation Address Register (Cnmwravaddr)
Non-Master CPU Fetch Access Violation Address This holds the address at which C28x CPU attempted a code fetch and the non-master CPU fetch access violation occurred. SPRUHE8E – October 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 534: Master Cpu Write Access Violation Address Register (Cmwravaddr)
Master CPU Fetch Access Violation Address This holds the address at which C28x CPU attempted a code fetch and the master CPU fetch access violation occurred. Internal Memory SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 535: Flash Controller Memory Module
Code Security Module to prevent access to the flash by unauthorized persons (refer to the System Control and Interrupts chapter for details) 5.3.2 Flash Tools Texas Instruments provides the following tools for flash: • Code Composer Studio V6.x - the development environment with integrated flash plugin •...
Page 536: Default Flash Configuration
Field description Size (bytes) 0x681000 OTPSECLOCK Security Lock 0x68100C Z2_FLASH_ENTRY_POINT Zone 2 Flash Entry point 0x681010 EMACID[31:0] Ethernet Mac address 0x681014 EMACID[63:32] Internal Memory SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 537: Flash Module Controller (Fmc)
C28x flash bank independently of each other. The shared charge pump module has its own independent power up/down timers as well. SPRUHE8E – October 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 538 FMC’s PMPPWR bit. As the pump is shared between M3-FMC and C28x-FMC, the effective PAGP value used when powering down the pump will be of the FMC (out of M3- Internal Memory SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 539: Flash And Otp Performance
(i.e., maximum flash clock frequency with one wait state - FCLKmax). SPRUHE8E – October 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 540: Flash Cache Mode
PROG_CACHE_EN bit in the FRD_INTF_CTRL register enables this cache mode. This flash prefetch and cache mechanisms are independent of the CPU pipeline. Internal Memory SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 541 When FSM interface is active for erase/program operations, data in the program cache and data cache in FMC will be invalidated. SPRUHE8E – October 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 542 If an instruction prefetch is already in progress when a data read operation is initiated, then the data read will be stalled until the prefetch completes. Internal Memory SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 543: Flash Prefetch Mode
When FSM interface is active for erase/program operations, data in the prefetch buffers and data cache in FMC will be flushed. SPRUHE8E – October 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 544: Erase/Program Flash
2. Set the banks to remain powered up by writing 3 to bits 0:1 of the FBFALLBACK register. 3. Turn on read margin 0 or 1 by writing 1 or 2 to the FSPRD register. Internal Memory SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 545: Error Correction Code (Ecc) Protection
The Flash API uses hardware ECC logic in the device to generate the ECC data for the given flash data. The Flash plugin and UniFlash use Flash APIs to generate and program ECC data. SPRUHE8E – October 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 546: Ecc Logic Inputs And Outputs
ECC logic will be bypassed when the 64 data bits and the associated ECC bits fetched from the bank are either all ones or zeros. Internal Memory SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 547 ERR_INTCLR register, an error interrupt will not come again, as this is an edge- based interrupt. SPRUHE8E – October 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 548 NMI will occur continuously until the ECC test mode is disabled. Once the above ECC test mode registers are written by the user: Internal Memory SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 549: Reserved Locations Within Flash And Otp
CPU pipeline. This must be done before the return-from-function call is made. 5. Return to the calling function which might reside in RAM or Flash/OTP and continue execution. SPRUHE8E – October 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 550: Procedure To Change The Flash Control Registers 5.4 Flash Registers
Status Register (Used with Flash API – Refer to Flash Application Programming Interface User’s Specification for details of this register) Reserved Reserved Internal Memory SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 551: Flash Registers Memory Map On Control Subsystem
Table 5-92. Flash Registers Memory Map on Control Subsystem Register Register Size (x8) Type C28x offset C28x Protection Reset source Acronym Description (0x8) Flash Control Registers 0x4000 SPRUHE8E – October 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 552 Clear Register ERR_CNT Error Counter EALLOW C28SYSRSTn Register ERR_THRESHO Error Threshold EALLOW C28SYSRSTn Register ERR_INTFLG Error Interrupt 0x10 EALLOW C28SYSRSTn Flag Register Internal Memory SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 553 C28SYSRSTn TEST High Register FECC_FOUTL_ Test Data Out 0x20 EALLOW C28SYSRSTn TEST Low Register FECC_STATUS ECC Status 0x22 EALLOW C28SYSRSTn Register SPRUHE8E – October 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 554: Master Subsystem Flash Control Registers
Read Margin 1 mode is disabled Read Margin 1 mode is enabled Read Margin 0 mode is disabled Read Margin 0 mode is enabled Internal Memory SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 555: Flash Bank Access Control Register (Fbac)
Note: If the bank and pump are not in active mode and an access is made, the value of this register is automatically changed to active. SPRUHE8E – October 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 556: Flash Bank Pump Control Register (Fbprdy)
PSLEEP = PSLEEP_REQ_ns / 2 / HCLK_period_ns PSLEEP = 20000/2/6.66 (in decimal) 15-1 Reserved Reserved Internal Memory SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 557: Flash Bank Pump Control Register 2 (Fpac2)
BANKID. Controls the bank on which the Flash FSM operations will be performed. For these devices, the value of this field will be 0 as there is only one bank in Master subsystem. SPRUHE8E – October 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 558: Seczonerequest(Sem) Register
Also, if sectors belonging to zone2 needs to be programmed or erased then SEM should be 10 or zone2 needs to be unlocked. Internal Memory SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 559: Flash Read Interface Control Register (Frd_Intf_Ctrl)
Prefetch enable. A value of 0 disables program cache and prefetch mechanism. A value of 1 enables program cache and prefetch mechanism. SPRUHE8E – October 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 560: Master Subsystem Flash Ecc/Error Log Registers
Table 5-105. Uncorrectable Error Address Register (UNC_ERR_ADDR) Field Descriptions Field Value Description 31-0 UNC_ERR_ADD Address at which an un-correctable error occurred, aligned to a 64-bit boundary Internal Memory SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 561: Error Status Register (Err_Status)
ERR_TYPE bit indicates a check bit or a data bit. If ERR_TYPE indicates a check bit error, the error position could range from 0 to 7, else it could range from 0 to 63. SPRUHE8E – October 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 562: Error Status Clear Register (Err_Status_Clr)
ECC logic test mode, ECC logic test mode has to be disabled prior to clearing the ERR_CNT using "Single Err Int Clear" bit. Internal Memory SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 563: Error Threshold Register (Err_Threshold)
SINGLE_ERR_INT interrupt is fired. When SINGLE_ERR_INT_CLR bit of ERR_INTCLR register is written a value of 1 this bit is cleared. SPRUHE8E – October 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 564: Error Interrupt Flag Clear Register (Err_Intclr)
31-0 FDATAL Low double word of selected 64-bit data. User-configurable bits 31:0 of the selected data blocks in ECC test mode. Internal Memory SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 565: Ecc Test Address Register (Faddr_Test)
Selects the ECC block on bits [127:64] of bank data. ECC_TEST_EN ECC test mode enable. ECC test mode disabled ECC test mode enabled SPRUHE8E – October 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 566: Test Data Out High Register (Fecc_Fouth_Test)
SINGLE_ERR Test mode ECC single bit error. When 1 indicates that the ECC test resulted in a single bit error. Internal Memory SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 567: Control Subsystem Flash Control Registers
Read Margin 1 mode is disabled Read Margin 1 mode is enabled Read Margin 0 mode is disabled Read Margin 0 mode is enabled SPRUHE8E – October 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 568: Flash Bank Access Control Register (Fbac)
Note: If the bank and pump are not in active mode and an access is made, the value of this register is automatically changed to active. Internal Memory SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 569: Flash Bank Pump Control Register (Fbprdy)
Note: The pump sleep down counter uses the same prescaled clock as Bank sleep down counter which is divided by 2 of input SYSCLK. 15-1 Reserved Reserved SPRUHE8E – October 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 570: Flash Bank Pump Control Register 2 (Fpac2)
Figure 5-121. Flash Read Interface Control Register (FRD_INTF_CTRL) Reserved DATA_CACHE_EN PROG_CACHE_EN R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Internal Memory SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 571: Control Subsystem Flash Ecc/Error Log Registers
Table 5-132. Uncorrectable Error Address Register (UNC_ERR_ADDR) Field Descriptions Field Value Description 31-0 UNC_ERR_ADD Uncorrectable error address. Address at which un-correctable error occurred, aligned to a 128 bit boundary. SPRUHE8E – October 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 572: Error Status Register (Err_Status)
ERR_TYPE bit indicates a check bit or a data bit. If ERR_TYPE indicates a check bit error, the error position could range from 0 to 7 else it could range from 0 to 63. Internal Memory SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 573: Error Status Clear Register (Err_Status_Clr)
Figure 5-129. Error Threshold Register (ERR_THRESHOLD) 16 15 Reserved THRESHOLD R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUHE8E – October 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 574: Error Interrupt Flag Register (Err_Intflg)
Single bit error interrupt flag clear. Writing a 1 to this bit will clear SINGLE_ERR_INT_FLG. Writes of 0 have no effect. Internal Memory SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 575: Data High Test Register (Fdatah_Test)
Figure 5-135. ECC Test Register (FECC_TEST) Reserved R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUHE8E – October 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 576: Ecc Control Register (Fecc_Ctrl)
Figure 5-138. Test Data Out Low Register (FECC_FOUTL_TEST) DATAOUTL LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Internal Memory SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 577: Ecc Status Register (Fecc_Status)
SINGLE_ERR Test mode ECC single bit error. When 1 indicates that the ECC test resulted in a single bit error. SPRUHE8E – October 2012 – Revised November 2019 Internal Memory Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 578: Rom Code And Peripheral Booting
................... C-Boot ROM Description ............Guidelines for Boot ROM Application Writers ..............Application Notes to Use Boot ROM ROM Code and Peripheral Booting SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 579: Introduction
– Use one of the available IPC commands to ask C-Boot ROM to boot from the control subsystem peripherals. SPRUHE8E – October 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 580: Device Boot Modes
NOTE: PF2_GPIO34 is reserved to be used as one of the boot mode input GPIOs at power-up or after reset. Users should take this into account when designing applications. ROM Code and Peripheral Booting SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 581: Device Boot Flow Diagram
Read Boot Mode GPIO Master subsystem boot as per boot mode ACIB interface ready SPRUHE8E – October 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 582: M-Boot Rom Description
IntDefaultHandler Bus Fault (5) 0x00000014 IntDefaultHandler Usage Fault (6) 0x00000018 IntDefaultHandler Reserved (7-10) 0x0000001C – 0x00000028 Reserved (0x00000000) ROM Code and Peripheral Booting SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 583: M-Boot Rom Version And Checksum Information
POR, then all of the master subsystem RAMs are zero-initialized and for all the other reset causes, only M-Boot ROM stack memory is zero-initialized. SPRUHE8E – October 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 584: M-Boot Rom Ram Usage
ECC is shared for these locations, so they must be programmed at the same time. 0x68 102C - 0x68 102F OTP ENTRY POINT ROM Code and Peripheral Booting SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 585: M-Boot Rom Entry Points
This entry point will be referred to as M_BOOT_ROM_CAN_BOOT_MODE_ENTRY_POINT further in this document. Please refer to Section 6.5.15.3.3 for more details on CAN boot mode data transfer protocol. SPRUHE8E – October 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 586: M-Boot Rom Clock Initialization
(PLLSYSCLK = MainOscClock/1) M3SSDIVSEL Divide by 4 Divide by 1 (M3SSCLK = PLLSYSCLK/4) (M3SSCLK = PLLSYSCLK = MainOscClk) ROM Code and Peripheral Booting SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 587: M-Boot Rom Gpio Assignments For Each Boot Mode
0(default) 0(default) Master(default DSP_CTRL Ouput PE2_GPIO26 0(default) 0(default) Master(default CAN Boot CAN0 CAN0_RX Input PB4_GPIO12 0(default) Master(default Mode SPRUHE8E – October 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 588 PM3_GPIO91 Alternate Master(default MII_TXD0 Output PM4_GPIO92 Alternate Master(default MII_RXD3 Input PL0_GPIO80 Alternate Master(default MII_RXD2 Input PL1_GPIO81 Alternate Master(default ROM Code and Peripheral Booting SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 589: M-Boot Rom Functional Flow
– Read Z1 CSM and Z2 CSM registers. Please refer to the Security section in the System Control and Interrupts chapter for more details. • Device Configuration Initialization SPRUHE8E – October 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 590 – If boot mode is boot_from_i2c0_master_mode • Download application data from I2C Slave connected to I2C0, the slave is addressed at 0x52. ROM Code and Peripheral Booting SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 591: M-Boot Rom Flow Diagram
Branch to the entry point address 6.5.11 M-Boot ROM Flow Diagram The M-Boot ROM flow diagram is shown below. SPRUHE8E – October 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 592: M-Boot Rom Flow Diagram
PORn and XRSn appropriately C-BootROM Bring control system out of reset Bring Analog system/CIB A-BootROM out of reset M_M3_1 ROM Code and Peripheral Booting SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 593 Start I2C Master IO loader and download application to RAM M3_APP Copy to M3 APP LOAD address Complete? Jump to APP_START_ADDRESS SPRUHE8E – October 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 594 NOTE: Boot-to-OTP option is not shown in this flow chart, but it is similar to boot-to-RAM option. The boot-ROM upon decoding the boot-to-OTP option from the boot-mode GPIO pins jumps to the M_BOOT_ROM_OTP_ENTRY_POINT. ROM Code and Peripheral Booting SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 595: M-Boot Rom Boot Status In Ram For Applications
If set, M-BootROM detected a C28 BIST ERR NMI If set, M-BootROM detected a M3 BIST ERR NMI If set, M-BootROM detected a Missing clock NMI SPRUHE8E – October 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 596: M-Boot Rom Reset Cause Handling
Log the error in boot status and configure WDT0 and loop and let device reset on WDT0 timeout. ROM Code and Peripheral Booting SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 597 PA3_GPIO3, peripheral MODE -1 SSI0_CLK PA2_GPIO2, peripheral MODE -1 SSI0_TX PA5_GPIO5, peripheral MODE -1 SSI0_RX PA4_GPIO4, peripheral MODE -1 SPRUHE8E – October 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 598 This allows the sender to re-transmit the previous packet. ROM Code and Peripheral Booting SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 599: M-Boot Rom Serial Boot Commands
COMMAND_GET_STATUS is sent to the microcontroller. COMMAND_RET_SUCCESS (= 0x40) COMMAND_RET_UNKNOWN_CMD (= 0x41) SPRUHE8E – October 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 600 The below function call sequence gives details of the flow when serial boot mode is selected on the device. • ResetIsr() • mbrom_init_device() • mbrom_master_system_init () • mbrom_control_system_init() ROM Code and Peripheral Booting SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 601 UART connection. The I2C interface also provides a standard interface, only uses two wires, and can operate at comparable speeds to the UART and SSI interfaces. SPRUHE8E – October 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 602 By using standard protocols, the bootloader will co-exist in a normal Ethernet environment without causing any problems (other than using a small amount of network bandwidth). ROM Code and Peripheral Booting SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 603 The below function call sequence gives details of the flow when EMAC boot mode is selected on the device. SPRUHE8E – October 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 604 The CAN bootloader provides a short list of commands that are used during the application download. The description of each of these commands is given below. ROM Code and Peripheral Booting SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 605: M-Boot Rom Can Boot Commands
If the application RUN address is different from application start address, then it is recommended to use “LM_API_UPD_RUN” command instead. SPRUHE8E – October 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 606 M-Boot ROM WIR Mode Check – Please refer to WIR Mode section in System Control and Interrupts chapter. • mbrom_get_bootmode() – ConfigureCAN(); • UpdaterCAN(); • mbrom_start_app(M_BOOT_ROM_CAN_BOOT_MODE_ENTRY_POINT) ROM Code and Peripheral Booting SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 607: Overview Of Parallel Gpio Bootloader Operation
(LSB). In this case, data is read from GPIO[9,8,5:0]. The 8-bit data stream is shown in Table 6-10. SPRUHE8E – October 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 608: Parallel Gpio Bootloader Handshake Protocol
This process is repeated for each data value to be sent. Figure 6-7 shows an overview of the Parallel GPIO bootloader flow. ROM Code and Peripheral Booting SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 609: Parallel Gpio Mode Overview
SPRUHE8E – October 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 610: Parallel Gpio Mode - Host Transfer Flow
MSB and LSB into a single 16-bit value to be passed back to the calling routine. ROM Code and Peripheral Booting SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 611: 8-Bit Parallel Getword Function
M-Boot ROM WIR Mode Check – Please refer to WIR Mode section in the System Control and Interrupts chapter. • mbrom_get_bootmode() – o Parallel_Boot(); • mbrom_start_app(M_BOOT_ROM_PARALLEL_BOOT_MODE_ENTRY_POINT) SPRUHE8E – October 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 612 In this mode, M-Boot ROM configures the SSI0 peripheral as master and tries to boot from a SSI slave. The pins used in this boot mode are listed inTable 6-1. ROM Code and Peripheral Booting SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 613: M-Boot Rom Boot Modes 6.6 C-Boot Rom Description
ROM. The memory block is 32Kx16 in size and is located at 0x3F 8000 - 0x3F FFFF in both program and data space. SPRUHE8E – October 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 614 SARAM space. The floating-point math tables included in the boot ROM are used by the Texas Instruments™ C28x FPU Fast RTS Library (SPRC664). The C28x Fast RTS Library is a collection of optimized floating-point math functions for C programmers of the C28x with floating-point unit.
Page 615 > FPUTABLES, PAGE = 0, TYPE = NOLOAD, The fixed-point math tables included in the boot ROM are used by the Texas Instruments™ C28x™ IQMath Library - A Virtual Floating Point Engine (SPRC087). The 28x IQmath Library is a collection of highly optimized and high precision mathematical functions for C/C++ programmers to seamlessly port a floating-point algorithm into fixed-point code on TMS320C28x devices.
Page 616 IQNatan2 N= 15, 20, 24, 29 • IQNcos N= 15, 20, 24, 29 • IQNdiv N= 15, 20, 24, 29 ROM Code and Peripheral Booting SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 617: C-Boot Rom Version And Checksum Information
PIE interrupt vector fetch, in which case C- Boot ROM sends an IPC message to the master subsystem as shown in Section 6.6.12.2 Section 6.6.1.3. SPRUHE8E – October 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 618: C-Boot Rom Vector Table Map
INT3 0x003FFFC6 0x00000046 INT4 0x003FFFC8 0x00000048 INT5 0x003FFFCA 0x0000004A INT6 0x003FFFCC 0x0000004C INT7 0x003FFFCE 0x0000004E INT8 0x003FFFD0 0x00000050 ROM Code and Peripheral Booting SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 619: Pie Vector Table In C-Boot Rom
INT2 (2) – INT14 (14) 0x00000D04 – 0x00000D1C cbrom_pie_isr_not_supported DLOGINT (15) 0x00000D1E cbrom_pie_isr_not_supported RTOSINT (16) 0x00000D20 cbrom_pie_isr_not_supported EMUINT (17) 0x00000D22 cbrom_pie_isr_not_supported SPRUHE8E – October 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 620: C-Boot Rom Ram Initialization
If code is bootloaded into this region there is no error checking to prevent it from corrupting the boot ROM stack. ROM Code and Peripheral Booting SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 621: C-Boot Rom Boot Modes
IPC commands is explained in detail in the subsequent sections of this chapter. Refer to Section 6.7 for more details on this procedure. SPRUHE8E – October 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 622: C-Boot Rom Entry Point
Entry point in this boot mode will be provided by the user or host system which is sending boot code to the device. Please refer to I2C Boot Data format for more details. ROM Code and Peripheral Booting SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 623 GPIOs used for each boot mode on C-Boot ROM. More details on the boot mode is given further below in this document. SPRUHE8E – October 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 624: C-Boot Rom Gpio Assignments For Boot Modes
Check the CRESC register and if the POR bit is set, then perform a RAM-INIT on all control subsystem ROM Code and Peripheral Booting SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 625 Set Boot Status for Master applications to read • Enter Low Power IDLE mode. The C-Boot ROM flow chart is shown below. SPRUHE8E – October 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 626: C-Boot Rom Flow Chart
EMU1==1 Install MTOCIPCINT1 Interrupt Service Routine Enable PIE Go to IDLE mode; Wake up to handle IPC interrupts ROM Code and Peripheral Booting SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 627 MTOCIPCFLG[0] is cleared by C-Boot ROM, in error cases. Figure 6-12 shows the procedure to be followed by the master subsystem application. SPRUHE8E – October 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 628: Master Subsystem Application Procedure To Send Ipc To C-Boot Rom
<to clear the IPCFLG which is not cleared by C-Boot ROM> 6.6.9.2 Procedure Followed by C-Boot ROM to Handle IPC Commands From Master - ROM Code and Peripheral Booting SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 629 Figure 6-13 explains how C-Boot ROM MTOCIPCINT1 handler - cbrom_mtoc_ipc_int1_isr, follows to service IPC command from Master. SPRUHE8E – October 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 630: C-Boot Rom Handling On Mtocipc
IDLE Mode Handling another IPC == FALSE Branch Command or Boot Command Branch address or boot app address ROM Code and Peripheral Booting SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 631: Mtoc Ipc Commands
Data read back 0x00 = Command EALLOW; _WRITE_PROTECTED_16 bit register MTOCIPCDATAW[ from the address success *(address) = data; 15:0] EDIS; SPRUHE8E – October 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 633: C-Boot Rom Nak/Error Status Returns For Mtocipccom
Note: The rest of the bits are reserved and user applications don’t care if these bits are set or reset. SPRUHE8E – October 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 634: C-Boot Rom Health Status
ROM. For ex: if MTOCIPCBOOTSTS == C_BOOTROM_BOOTSTS_CTOM_CONTROL_SYSTEM_READY, it means that C-Boot ROM is ready to accept MTOC IPC commands. ROM Code and Peripheral Booting SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 635: Ctom Ipc Messages
C-Boot ROM is waiting for a reset from the master subsystem, when this even occurs SPRUHE8E – October 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 636: C-Boot Reset Cause Handling
Table 6-23 explains the actions taken by C-Boot ROM in response to various events that can occur during boot. ROM Code and Peripheral Booting SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 637: C-Boot Rom Exceptions Handling
@0x3FFFBE will send an IPC message to master and wait in while(1) loop for master to handle the error state. SPRUHE8E – October 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 638 Execution will then continue at the entry point address as determined by the input data stream contents. ROM Code and Peripheral Booting SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 639: General Structure Of Source Program Data Stream In 16-Bit Mode
Last word of the last block of the source being loaded Block size of 0000h - indicates end of the source program SPRUHE8E – October 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 640 (LSW). The bootloaders take this into account when loading an 8-bit data stream. ROM Code and Peripheral Booting SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 641: Lsb/Msb Loading Sequence In 8-Bit Data Stream
MSB: Last word of the last block LSB: 00h MSB: 00h - indicates the end of the source SPRUHE8E – October 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 642 8-bit or 16-bit key value, or if the value is not valid for the given boot mode then the load will abort. ROM Code and Peripheral Booting SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 643: Bootloader Basic Transfer Procedure
See the info specific to a particular bootloader for any limitations. In 8-bit mode, the LSB of the 16-bit word is read first followed by the MSB. SPRUHE8E – October 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 644: Overview Of Copydata Function
ROM SCITXDA source) The SCI-A loader uses following pins: • SCIRXDA on GPIO36 • SCITXDA on GPIO35 ROM Code and Peripheral Booting SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 645: Overview Of Sci_Boot Function
Disable SCI FIFOs Prime SCI-A baud register Read EntryPoint address Enable autobaud detection Call CopyData Autobaud lock Return EntryPoint SPRUHE8E – October 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 646: Overview Of Sci_Getworddata Function
SCIA_GetWordData Received Read LSB Data Echoback LSB Received to host Read MSB Echoback MSB Return MSB:LSB to host ROM Code and Peripheral Booting SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 647: Spi Loader
Data for this section. Blocks of data in the format size/destination address/data as shown in the generic data stream description SPRUHE8E – October 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 649: Data Transfer From Eeprom Flow
Figure 6-22. Overview of SPIA_GetWordData Function Data Send dummy SPIA_GetWordData Received character Read LSB Data Send dummy Received character Read MSB Return MSB:LSB SPRUHE8E – October 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 650: Eeprom Device At Address 0X50
The input frequency to the device must be in the appropriate range. • The EEPROM must be at slave address 0x50. ROM Code and Peripheral Booting SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 651: Overview Of I2C_Boot Function
(I2C_Get Word). If a non acknowledgment is received during the data read messages, the I2C bus will hang. Table 7-3 shows the 8-bit data stream used by the I2C. SPRUHE8E – October 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 652: Random Read
Figure 6-26. Sequential Read SDA LINE 0 0 0 1 0 Device DATA BYTE n DATA BYTE n+1 Address ROM Code and Peripheral Booting SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 653: Overview Of Parallel Gpio Bootloader Operation
(LSB). In this case, data is read from GPIO[9,8,5:0]. The 8-bit data stream is shown in Table 6-28. SPRUHE8E – October 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 654: Parallel Gpio Bootloader Handshake Protocol
This process is repeated for each data value to be sent. Figure 6-29 shows an overview of the Parallel GPIO bootloader flow. ROM Code and Peripheral Booting SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 655: Parallel Gpio Mode Overview
SPRUHE8E – October 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 656: Parallel Gpio Mode - Host Transfer Flow
(MSB). It then combines the MSB and LSB into a single 16-bit value to be passed back to the calling routine. ROM Code and Peripheral Booting SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 657: 8-Bit Parallel Getword Function
The flow diagrams and procedures listed below in this section explain the minimum things that should be done in order to successfully boot the control subsystem. SPRUHE8E – October 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 658: Master Subsystem Application Flow To Start C-Boot Rom Loaders
ODE = MTOCIPCBOOTMODE ODE = ODE = ODE = = BOOT_FROM_RAM BOOT_FROM_PAR BOOT_FROM_SCI BOOT_FROM_I2C BOOT_FROM_SPI ALLEL MTOCIPCSET = 0x80000001 ROM Code and Peripheral Booting SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 659: Build A Binary Image For Bootload Using M-Boot Rom
M-Boot ROM. C:/Program Files/Texas Instruments/ccsv4/utils/tiobj2bin/tiobj2bin.bat C:/Program Files/Texas Instruments/ccsv4/tools/compiler/tms470/bin/ofd470.exe C:/Program Files/Texas Instruments/ccsv4/tools/compiler/tms470/bin/hex470.exe C:/Program Files/Texas Instruments/ccsv4/utils/tiobj2bin/mkhex4bin.exe SPRUHE8E – October 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 660: Lm Flash Programmer Configuration Screen
2. Select either UART or Ethernet interface as shown below, depending on which interface he is using to boot load data. ROM Code and Peripheral Booting SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 661: Lm Flash Programmer Interface Selection Screen
6.8.1.2.1 Using the LM FLASH Programmer to Send Data to the M-Boot ROM UART0 Interface – Serial Bootload Option 1. Select the UART interface and configure the HOST COM Port Baud Rate as needed. SPRUHE8E – October 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 662: Lm Flash Programmer Serial Interface Configuration Screen
MCU, but will send the RESET packet to the M-Boot ROM bootloader which will start executing the application code just downloaded. ROM Code and Peripheral Booting SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 663: Lm Flash Programmer Binary Image Selection Screen
Concerto device, and the Client IP Address field should be filled with a proper IP address that the user wants to assign to the device. SPRUHE8E – October 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 664: Lm Flash Programmer Emac Interface Selection Screen
Note: There is no way for the user to control where in the master subsystem RAM, the application should get loaded. It is fixed at M_BOOT_ROM_RAM_ENTRY_POINT as explained in Section 6.5.7.5 ROM Code and Peripheral Booting SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 665: Flash Programmer Emac Bootload Binary Image Selection Screen
It can be useful to check this file to make sure SPRUHE8E – October 2012 – Revised November 2019 ROM Code and Peripheral Booting Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 666: Bootloader Options
Specify the value for the I2CCLKL register. This value will be loaded and take effect after all I2C options are loaded, prior to reading data from the EEPROM. ROM Code and Peripheral Booting SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 667 ........................... Topic Page ..................... Introduction ................... ePWM Submodules ..............Applications to Power Topologies ......................Registers SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 669 Each ePWM module is connected to the input/output signals shown in Figure 7-1. The signals are described in detail in subsequent sections. SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 670: Multiple Epwm Modules
Each ePWM module consists of eight submodules and is connected within a system via the signals shown in Figure 7-2. C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 671: Submodules And Signal Connections For An Epwm Module
Whichever event triggers the start of conversion is configured in the Event-Trigger submodule of the ePWM. SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 672: Epwm Submodules And Critical Internal Signal Interconnects
Each submodule is described in detail in its respective section. C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 673 7-1. Each register set is duplicated for each instance of the ePWM module. The start address for each ePWM register file instance on a device is specified in the appropriate data manual. SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 674: Epwm Module Control And Status Register Set Grouped By Submodule
These registers only exist in the ePWM1 register space. They cannot be accessed from any other ePWM module's register space. C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 675 0x70-0x7F contains dual-mapped frequently-used control registers from lower page in order to accommodate minimal DP pointer switching. SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 676: Epwm Module Control And Status Register Set Grouped By Submodule (Upper Page)
[if exisiting] and their behaviour in shadow/immediate mode with respect to a Read or Write operation. In Immediate Mode: C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 677 DBFED 0x11 Shadow Shadow DBFEDM 0x53 Shadow Shadow CMPC 0x69 Shadow Shadow CMPD 0x6B Shadow Shadow SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 678: Submodule Configuration Parameters
• Bypass the PWM-chopper module entirely. In this case the PWM waveform is passed through without modification. C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 679 These examples use the constant definitions in the device EPwm_defines.h file in the device-specific header file and peripheral examples software package. SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 680: Time-Base Submodule
Configure the rate of the time-base clock; a prescaled version of the CPU system clock (SYSCLKOUT). This allows the time-base counter to increment/decrement at a slower rate. C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 681: Time-Base Submodule Registers
Width Modulator (HRPWM) section of this manual. Refer to the device-specific data manual to determine which ePWM instances include this feature. SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 682: Time-Base Submodule Signals And Registers
This signal is generated whenever the counter value is zero. That is when TBCTR equals 0x00. C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 683 When it reaches zero, the time-base counter is reset to the period value and it begins to decrement once again. SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 684: Time-Base Frequency And Period
PRDLDSYNC bit is valid only if TBCTL[PRDLD] = 0. By default the TBPRD shadow register is enabled. The sources for the SYNC input is explained in Time-Base Counter Synchronization section C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 685: Time-Base Counter Synchronization Scheme 4
Please refer to the device specific data manual to determine which modules are available on a particular device. SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 686 2. Set TBCLKSYNC = 0. This will stop the time-base clock within any enabled ePWM module. 3. Configure the prescaler values and desired ePWM modes. 4. Set TBCLKSYNC = 1. C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 687 To illustrate the operation of the first three modes, the following timing diagrams show when events are generated and how the time-base responds to an EPWMxSYNCI signal. SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 688: Time-Base Up-Count Mode Waveforms
TBCTR[15:0] 0xFFFF TBPRD (value) TBPHS (value) 0000 EPWMxSYNCI CTR_dir CTR = zero CTR = PRD CNT_max C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 689: Time-Base Down-Count Mode Waveforms
(value) TBPHS (value) 0x0000 EPWMxSYNCI CTR_dir DOWN DOWN DOWN CTR = zero CTR = PRD CNT_max SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 690: Time-Base Up-Down Count Waveforms, Tbctl[Phsdir = 1] Count Up On Synchronization Event
Digital Compare PIEERR (DC) Signals COMPxOUT GPTRIP Figure 7-13 shows the basic structure of the counter-compare submodule. C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 691: Counter-Compare Submodule Registers
Modulator (HRPWM) section of this manual. Refer to the device-specific data manual to determine which ePWM instances include this feature. SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 692: Detailed View Of The Counter-Compare Submodule
TBCTR = CMPC CTR = CMPD Time-base counter equal to the active counter-compare D value TBCTR = CMPD C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 693 1. CTR = CMPC: Time-base counter equal to counter-compare C register (TBCTR = CMPC). 2. CTR = CMPD: Time-base counter equal to counter-compare D register (TBCTR = CMPD). SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 694 Figure 7-14 through Figure 7-17 show when events are generated and how the EPWMxSYNCI signal interacts. C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 695: Counter-Compare Event Waveforms In Up-Count Mode
This can lead to a compare event being skipped. This skipping is considered normal operation and must be taken into account. SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 696: Counter-Compare Events In Down-Count Mode
TBPRD (value) CMPA (value) CMPB (value) TBPHS (value) 0x0000 EPWMxSYNCI CTR = CMPA CTR = CMPB C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 697: Counter-Compare Events In Up-Down-Count Mode, Tbctl[Phsdir = 0] Count Down On Synchronization Event
7.2.4 Action-Qualifier (AQ) Submodule Figure 7-18 shows the action-qualifier (AQ) submodule (see shaded block) in the ePWM system. SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 698: Action-Qualifier Submodule
Action Qualifier Control Mirror Register For Output B AQSFRCM 0x75 Action Qualifier Software Force Mirror Register C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 699: Action-Qualifier Submodule Inputs And Outputs
The possible actions imposed on outputs EPWMxA and EPWMxB are: • Set High: Set output EPWMxA or EPWMxB to a high level. SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 700: Possible Action-Qualifier Actions For Epwmxa And Epwmxb Outputs
TB Counter equals: Actions force Comp Comp Zero Period Do Nothing Clear Low Set High Toggle C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 701: Action-Qualifier Event Priority For Up-Down-Count Mode
(TBCTR=CMPA or CMPB). If CMPA/CMPB > TBPRD, then the event will not occur. SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 702 Compare when using Shadow to Active Load of Action Qualifier Output A/B Control Register on TBCTR = 0 boundary. C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 703: Aqctlr[Shdwaqamode]
TBCTL[SWFSYNC] AQCTLB(16) Active Reg AQCTLR AQCTLB(16) [LDAQBMODE] Shadow Reg AQCTLR[SHDWAQBMODE] CTR = PRD CTR = Zero SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 704 TBPRD-1. This means there will always be a pulse of at least one TBCLK cycle in a PWM period which, when very short, tend to be ignored by the system. C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 705: Up-Down-Count Mode Symmetrical Waveform
Up-Down means Count-up-and-down mode, Up means up-count mode and Dwn means down-count mode • Sym = Symmetric, Asym = Asymmetric SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 706: Up, Single Edge Asymmetric Waveform, With Independent Modulation On Epwmxa And Epwmxb-Active High
// = = = = = = = = = = = = = = = = = = = = = = = = EPwm1Regs.CMPA.half.CMPA = Duty1A; // adjust duty for output EPWM1A C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 707: Up, Single Edge Asymmetric Waveform With Independent Modulation On Epwmxa And Epwmxb-Active Low
Example 7-2 contains a code sample showing initialization and run time for the waveforms in Figure 7-25. SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 708: Up-Count, Pulse Placement Asymmetric Waveform With Independent Modulation On Epwmxa
Figure 7-26. Use the code in Example 7-5 to define the headers. C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 709 // = = = = = = = = = = = = = = = = = = = = = = = = EPwm1Regs.CMPA.half.CMPA = EdgePosA; // adjust duty for output EPWM1A only EPwm1Regs.CMPB = EdgePosB; SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 710: Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation On Epwmxa And Epwmxb - Active Low
EPwm1Regs.CMPA.half.CMPA = Duty1A; // adjust duty for output EPWM1A EPwm1Regs.CMPB = Duty1B; // adjust duty for output EPWM1B C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 711: Up-Down-Count, Dual Edge Symmetric Waveform, With Independent Modulation On Epwmxa And Epwmxb - Complementary
EPwm1Regs.CMPA.half.CMPA = Duty1A; // adjust duty for output EPWM1A EPwm1Regs.CMPB = Duty1B; // adjust duty for output EPWM1B SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 712: Up-Down-Count, Dual Edge Asymmetric Waveform, With Independent Modulation On Epwmxa-Active Low
// = = = = = = = = = = = = = = = = = = = = = = = = EPwm1Regs.CMPA.half.CMPA = EdgePosA; // adjust duty for output EPWM1A only EPwm1Regs.CMPB = EdgePosB; C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 713: Dead_Band Submodule
The following list shows the distinct difference between type 1 and type 2 modules with respect to Dead Band operating modes SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 714 Controlling and Monitoring the Dead-Band Submodule The dead-band submodule operation is controlled and monitored via the following registers: C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 715: Dead-Band Generator Submodule Registers
SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 716: Configuration Options For The Dead-Band Submodule
EPWMxA and EPWMxB Passed Through (No Delay) Active High Complementary (AHC) Active Low Complementary (ALC) Active High (AH) Active Low (AL) C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 717: Additional Dead-Band Operating Modes
When this bit is set to 1, user should always either set OUT_MODE bits such that Apath = InA or OUTSWAP bits such that EPWMxA=Bpath. Otherwise, EPWMxA will be invalid. SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 718: Dead-Band Waveforms For Typical Cases (0% < Duty < 100%)
Delayed (FED) Active High Complementary (AHC) Active Low Complementary (ALC) Active High (AH) Active Low (AL) C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 719: Dead-Band Delay Values In Μs As A Function Of Dbfed And Dbred
When half-cycle clocking is enabled, the formula to calculate the falling-edge-delay and rising-edge-delay becomes: FED = DBFED × T TBCLK RED = DBRED × T TBCLK SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 720: Pwm-Chopper Submodule
The one-shot width is programmed via the OSHTWTH bits. The PWM-chopper submodule can be fully disabled (bypassed) via the CHPEN bit. C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 721: Pwm-Chopper Submodule Operational Details
Details of the one-shot and duty-cycle control are discussed in the following sections. Figure 7-35. Simple PWM-Chopper Submodule Waveforms Showing Chopping Action Only EPWMxA EPWMxB PSCLK EPWMxA EPWMxB SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 722: Pwm-Chopper Submodule Waveforms Showing The First Pulse And Subsequent Sustaining Pulses
SYSCLKOUT = 80 MHz OSHTWTHz Pulse Width (hex) (nS) 1000 1100 1200 1300 1400 1500 1600 C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 723: Pwm-Chopper Submodule Waveforms Showing The Pulse Width (Duty Cycle) Control Of Sustaining Pulses
PSCLK PSCLK period PSCLK Period 62.5% 87.5% 37.5% 12.5% Duty Duty Duty Duty Duty Duty Duty SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 724: Trip-Zone Submodule
Software-forced tripping is also supported. • The trip-zone submodule can be fully bypassed if it is not required. C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 725: Trip-Zone Submodule Registers
When a one-shot trip event occurs, the action specified in the TZCTL[TZA] and TZCTL[TZB] bits is SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 726 TZCTL register bit fields. One of four possible actions, shown in Table 7-21, can be taken on a trip event. C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 727: Possible Actions On A Trip Event
DCAEVT1/2 and DCBEVT1/2 signals are described in further detail in Section 7.2.9. SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 728: Trip-Zone Submodule Mode Control Logic
Async Sync Clear Trip TZFLG[OST] DCAEVT1.force DCBEVT1.force One-Shot (OSHT) Trip Events TZSEL[OSHT1 to OSHT6, DCAEVT1, DCBEVT1] C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 729: Trip-Zone Submodule Interrupt Logic
ADC when a selected event occurs. Figure 7-41 illustrates where the event-trigger submodule fits within the ePWM system. SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 730: Trigxsel Trigger Options
00111 EPWM1SYNC 01000 EPWM2SOCA EPWM2 01001 EPWM2SOCB 01010 EPWM2SYNC 01011 EPWM3SOCA EPWM3 01100 EPWM3SOCB 01101 EPWM3SYNC C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 731: Event-Trigger Submodule Inter-Connectivity Of Adc Start Of Conversion
ADC start of conversion. The event-trigger prescaling logic can issue Interrupt requests and ADC start of conversion at: • Every event • Every second event • Up to Every fifteenth event SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 732: Event-Trigger Submodule Showing Event Inputs And Prescaled Outputs
ETCNTINIT - These bits allow you to initialize INT/SOCA/SOCB counters on SYNC events (or software force) with user programmed value. C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 733 Writing an INTPRD value that is LESS than the current counter value will result in undefined behavior (that is, INTCNT stops counting because INTPRD is below INTCNT, and interrupt will never fire). SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 734: Event-Trigger Interrupt Generator
(DC) submodule. The SOCACNT2 initialization scheme is very similar to the interrupt generator with respective enable, value initialize and SYNC or software force options. C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 735: Event-Trigger Soca Pulse Generator
ETSEL[SOCBSELCMP] The DCBEVT1.soc signals are signals generated by the Digital compare (DC) submodule in Section 7.2.9. SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 736: Digital-Compare Submodule High-Level Block Diagram
[DCAHTRIPSEL, DCALTRIPSEL, DCBHTRIPSEL, DCBLTRIPSEL] The ECAP input signals are sourced from the GPTRIP signals as shown in Figure 7-48. C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 737: Gpio Mux-To-Trip Input Connectivity
DCAH/L and DCBH/L signals trigger events which can then either be filtered or fed directly to the trip- SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 738: Digital Compare Submodule Registers
The TZDCSEL register is part of the trip-zone submodule but is mentioned again here because of its functional significance to the digital compare submodule. C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 739 The diagrams below show how the DCAEVT1, DCAEVT2 or DCEVTFLT signals are processed to generate the digital compare A event force, interrupt, soc and sync signals. SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 740: Dcaevt1 Event Triggering
Figure 7-50. DCAEVT2 Event Triggering DCACTL[EVT2SRCSEL] DCACTL[EVT2FRCSYNCSEL] DCEVTFILT Async DCAEVT2 DCAEVT2.force Sync TZEINT[DCAEVT2] TBCLK TZFRC[DCAEVT2] Latch DCAEVT2.inter Clear TZFLG[DCAEVT2] TZCLR[DCAEVT2] C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 741: Dcbevt1 Event Triggering
ADC start-of-conversion. The event filtering can also capture the TBCTR value of the trip event. The diagram below shows the details of the event filtering logic. SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 742: Event Filtering
CTR = 0 or CTR = PRD pulse. C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 743: Blanking Window Timing Diagram
CTR = 0 Offset(n) Offset(n+1) BLANKWDW Window(n) Window(n+1) Offset(n) Offset(n+1) BLANKWDW Window(n) Window(n+1) Offset(n) Offset(n+1) BLANKWDW Window(n+1) Window(n) SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 744: Simplified Epwm Module
SyncIn strobe input or choose to ignore it, i.e., via the enable switch. Although various combinations are possible, the two most common—master module and slave module modes—are shown in Figure 7-56. C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 745: Epwm1 Configured As A Typical Master, Epwm2 Configured As A Slave
Figure 7-57; note that only three waveforms are shown, although there are four stages. SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 746: Control Of Four Buck Stages. Here F
EPWM4A CTR=CMPB SyncOut NOTE: Θ = X indicates value in phase register is a "don't care" C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 747: Buck Waveforms For (Note: Only Three Bucks Shown Here)
EPWM3A Indicates this event triggers an ADC start Indicates this event triggers an interrupt of conversion SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 748 EPwm2Regs.CMPA.half.CMPA = 700; // adjust duty for output EPWM2A EPwm3Regs.CMPA.half.CMPA = 500; // adjust duty for output EPWM3A C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 749: Control Of Four Buck Stages
Slave EPWM2A Phase reg SyncIn Φ=X EPWM2A Vin4 Vout4 EPWM2B CTR=zero CTR=CMPB Buck #4 SyncOut EPWM2B SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 750: Pwm1) )
Figure 7-60. Buck Waveforms for Figure 7-59 (Note: F PWM2 PWM1) EPWM1A EPWM1B EPWM2A EPWM2B C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 751 EPwm2Regs.CMPA.half.CMPA = 500; // adjust duty for output EPWM2A EPwm2Regs.CMPB = 300; // adjust duty for output EPWM2B SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 752 EPWM1B SyncOut Slave Phase reg SyncIn DC_bus Φ=0° EPWM2A out2 EPWM2B CTR=zero EPWM2A CTR=CMPB SyncOut EPWM2B C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 753: Pwm1 )
Figure 7-62. Half-H Bridge Waveforms for Figure 7-61 (Note: Here F PWM2 PWM1 EPWM1A EPWM1B Pulse Center EPWM2A EPWM2B Pulse Center SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 754 1, 2, 3 (also all equal). C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 755: Control Of Dual 3-Phase Inverter Stages As Is Commonly Used In Motor Control
3 phase motor SyncOut Slave Phase reg SyncIn 3 phase inverter #2 Φ=0° EPWM6A EPWM6B CTR=zero CTR=CMPB SyncOut SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 756: 3-Phase Inverter Waveforms For (Only One Inverter Shown)
Figure 7-64. 3-Phase Inverter Waveforms for Figure 7-63 (Only One Inverter Shown) EPWM1A EPWM1B Φ2=0 EPWM2A EPWM2B Φ3=0 EPWM3A EPWM3B C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 757 EPwm2Regs.CMPA.half.CMPA = 600; // adjust duty for output EPWM2A EPwm3Regs.CMPA.half.CMPA = 700; // adjust duty for output EPWM3A SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 758: Configuring Two Pwm Modules For Phase Control
SyncIn pulse (CTR = PRD), the value of TBPHS = 200 is loaded into the slave TBCTR register so the slave time-base is always leading the master's time-base by 120°. C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 759: Timing Waveforms Associated With Phase Control Between 2 Modules
TBPHS(3,3) = 400 (i.e., Phase value for Slave module 3) Figure 7-68 shows the waveforms for the configuration in Figure 7-67. SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 760: Control Of A 3-Phase Interleaved Dc/Dc Converter
Φ=120° EPWM2A EPWM2B CTR=zero CTR=CMPB SyncOut Slave Phase reg SyncIn Φ=240° EPWM3A EPWM3B CTR=zero CTR=CMPB SyncOut C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 761: 3-Phase Interleaved Dc/Dc Converter Waveforms For
Figure 7-68. 3-Phase Interleaved DC/DC Converter Waveforms for Figure 7-67 EPWM1A EPWM1B Φ2=120° TBPHS (=300) EPWM2A EPWM2B Φ2=120° TBPHS (=300) EPWM3A EPWM3B SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 762 EPwm2Regs.CMPA.half.CMPA = 285; // adjust duty for output EPWM2A EPwm3Regs.CMPA.half.CMPA = 285; // adjust duty for output EPWM3A C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 763: Pwm2 Pwm1)
SyncOut Slave Phase reg SyncIn EPWM2A Φ=Var° EPWM1B EPWM2B EPWM2B CTR=zero CTR=CMPB SyncOut Var = Variable SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 764: Zvs Full-H Bridge Waveforms
1200 EPWM1A ZVS transition Power phase EPWM1B ZVS transition Φ2=variable TBPHS =(1200−Φ2) EPWM2A EPWM2B Power phase C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 765 10-bit DAC can be used to provide a reference peak current at the negative SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 766: Peak Current Mode Control Of A Buck Converter
Figure 7-71 ePWM1 TBPRD Time base = 300 Increased DAC OUT/ Load COMP1- Isense DCAEVT2.force ePWM1A C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 767 30 @100MHz TBCLK), it is up to user to update it in real time to enhance the efficiency by adjusting enough time delay for soft switching. SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 768: Control Of Two Resonant Converter Stages
Indicates this event triggers an ADC Indicates this event triggers an interrupt start of conversion C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 769 EPwm1Regs.CMPA.half.CMPA= period_new value/2; // Update new CMPA EPwm1Regs.CMPB= period_new value/4; // Update new CMPB // Update new CMPB SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 770: Time-Base Period And Mirror 2 Register (Tbprd / Tbprdm2)
Figure 7-77. Time-Base Period Mirror Register (TBPRDM) TBPRD R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 771: Time-Base Period High-Resolution Mirror Register (Tbprdhrm)
Figure 7-79. Time-Base Phase Register and Mirror Register (TBPHS / TBPHSM) TBPHS R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 772: Time-Base Phase High-Resolution Register And Mirror Register (Tbphshr / Tbphshrm)
R/W-0 R/W-0 R/W-11 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 773: Time-Base Control Register (Tbctl) Field Descriptions
CTR = CMPB : Time-base counter equal to counter-compare B (TBCTR = CMPB) Disable EPWMxSYNCO signal SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 774 These bits set the time-base counter mode of operation as follows: Up-count mode Down-count mode Up-down-count mode Stop-freeze counter operation (default on reset) C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 775: Time-Base Status Register (Tbsts)
This register is EALLOW protected. This register is used with Type 1 ePWM modules (support high-resolution period) only. SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 776: Time-Base Control Register 2 (Tbctl2)
R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 777: Epwmx Link Register (Epwmxlink) Field Descriptions
1010 ePWM9 All other values are reserved and do nothing (i.e., register is linked to itself). SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 778 1010 ePWM9 All other values are reserved and do nothing (i.e., register is linked to itself). C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 779: Counter-Compare Control Register (Cmpctl)
Immediate mode. Only the active compare register is used. All writes and reads directly access the active register for immediate compare action SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 780: Compare Control Register (Cmpctl2)
Immediate mode – only the Active compare register is used. All writes/reads via the CPU directly access the Active register for immediate “Compare action”. C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 781: Compare A High-Resolution And Mirror 2 Register (Cmpahr / Cmpahrm2 )
Shadowing is enabled and disabled by the CMPCTL[SHDWAMODE] bit as described for the CMPA register. Reserved Reserved for TI Test SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 782: Counter-Compare A And Mirror 2 Register (Cmpa / Cmpam2)
Figure 7-92. Counter-Compare A Mirror Register (CMPAM) CMPA R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 783: Counter-Compare B Register (Cmpbm)
Figure 7-94. Counter-Compare B Register (CMPB) CMPB R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 784: Counter-Compare C Register (Cmpc)
Figure 7-96. Counter-Compare D Register (CMPD) CMPD R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 785: Compare B High-Resolution Register (Cmpbhr)
By default writes to this register are shadowed. Shadowing is enabled and disabled by the CMPCTL[SHDWBMODE] bit as described for the CMPBM register. Reserved Reserved for TI test. SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 786: Action-Qualifier Output A Control Register And Mirror Register (Aqctla / Aqctlam)
Toggle EPWMxA output: low output signal will be forced high, and a high signal will be forced low. C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 787: Action-Qualifier Output B Control Register And Mirror Register (Aqctlb / Aqctlbm)
Toggle EPWMxB output: low output signal will be forced high, and a high signal will be forced low. SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 788: Action-Qualifier Software Force Register And Mirror Register (Aqsfrc / Aqsfrcm)
Toggle (Low -> High, High -> Low) Note: This action is not qualified by counter direction (CNT_dir) C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 789: Action-Qualifier Continuous Software Force Register And Mirror Register (Aqcsfrc / Aqcsfrcm)
Forces a continuous low on output A Forces a continuous high on output A Software forcing is disabled and has no effect SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 790: Action Qualifier Control Register (Aqctlr)
Load on either CTR = Zero or CTR = PRD Freeze (no loads possible) Note: has no effect in Immediate mode. C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 791: Dead-Band Generator Control Register (Dbctl)
Shadow mode. Operates as a double buffer. All writes via the CPU access the Shadow register. Default at Reset is Immediate mode (for compatibility with legacy). SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 792 Bpath = InB (delay is by-passed for B signal path) DBM is fully enabled (i.e. both RED and FED active) C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 793: Dead-Band Generator Rising Edge Delay And Mirror Register (Dbred / Dbredm)
DBFEDHR Reserved R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 794: Dead Band Falling Edge Delay High-Resolution Register (Dbfedhr) Field Descriptions
DBCTL[SHDWDBFEDMODE] bit as described for the DBFED register. Reserved Reserved for TI Test C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 795: Pwm-Chopper Control Register (Pcctl)
15 x SYSCLKOUT / 8 wide ( = 1200 nS at 100 MHz SYSCLKOUT) 1111 16 x SYSCLKOUT / 8 wide ( = 1280 nS at 100 MHz SYSCLKOUT) SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 796 Table 7-59. PWM-Chopper Control Register (PCCTL) Bit Descriptions (continued) Field Value Description CHPEN PWM-chopping Enable Disable (bypass) PWM chopping function Enable chopping function C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 797: Trip-Zone Select Register (Tzsel)
Disable DCAEVT2 as a CBC trip source for this ePWM module Enable DCAEVT2 as a CBC trip source for this ePWM module SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 798: Trip-Zone Control Register (Tzctl)
Force EPWMxA to a high state. Force EPWMxA to a low state. Do Nothing, trip action is disabled C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 799: Trip-Zone Enable Interrupt Register (Tzeint)
Disable cycle-by-cycle interrupt generation. Enable interrupt generation; a cycle-by-cycle trip event will cause an EPWMx_TZINT PIE interrupt. SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 800: Trip-Zone Flag Register (Tzflg)
Clearing all flag bits will prevent further interrupts. This bit is cleared by writing the appropriate value to the TZCLR register. C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 801: Trip-Zone Clear Register And Mirror Register (Tzclr / Tzclrm)
TZFLG[INT] bit is cleared and any of the other flag bits are set, then another interrupt pulse will be generated. Clearing all flag bits will prevent further interrupts. SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 802: Trip-Zone Force Register (Tzfrc)
R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 803: Trip Zone Digital Compare Event Select Register (Tzdcsel) Field Descriptions
DCAL = low, DCAH = don't care DCAL = high, DCAH = don't care DCAL = high, DCAH = low reserved reserved SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 804: Digital Compare Trip Select (Dctripsel)
TRIPIN14 1110 TRIPIN15 1111 Trip combination input (all trip inputs selected by DCALTRIPSEL register ORed together) C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 805: Digital Compare A Control Register (Dcactl)
Source Is Asynchronous Signal EVT1SRCSEL DCAEVT1 Source Signal Select Source Is DCAEVT1 Signal Source Is DCEVTFILT Signal SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 806: Digital Compare B Control Register (Dcbctl)
15-13 Reserved Reserved 12-8 Reserved Reserved for TI Test Reserved Reserved Reserved Reserved for TI Test C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 807: Digital Compare Capture Control Register (Dccapctl)
Figure 7-122. Digital Compare Counter Capture Register (DCCAP) DCCAP LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 808: Digital Compare Filter Offset Register (Dcfoffset)
The offset counter is not affected by the free/soft emulation bits. That is, it will always continue to count down if the device is halted by a emulation stop. C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 809: Digital Compare Filter Window Register (Dcfwindow)
R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 810: Digital Compare A High Trip Input Select (Dcahtripsel) Field Descriptions
Trip Input 1 not selected as combinational ORed input Trip Input 1 selected as combinational ORed input to DCAH mux C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 811: Digital Compare A Low Trip Input Select (Dcaltripsel) (Eallow-Protected)
Trip Input 3 not selected as combinational ORed input Trip Input 3 selected as combinational ORed input to DCAL mux SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 812: Digital Compare B High Trip Input Select (Dcbhtripsel) (Eallow-Protected)
Trip Input 6 not selected as combinational ORed input Trip Input 6 selected as combinational ORed input to DCBH mux C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 813: Digital Compare B Low Trip Input Select (Dcbltripsel) (Eallow-Protected)
Trip Input 9 not selected as combinational ORed input Trip Input 9 selected as combinational ORed input to DCBL mux SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 814 Trip Input 1 not selected as combinational ORed input Trip Input 1 selected as combinational ORed input to DCBL mux C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 815: Gpio Trip Input Select Register (Gptripxsel)
Reserved GPTRIPxSEL R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 816: Gpio Trip Input Select Register (Gptripxsel) Field Descriptions
000001 Select the GPIO1 ..111110 Select the GPIO62 111111 Select the GPIO63 C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 817: Event-Trigger Selection Register (Etsel)
Enable event: time-base counter equal to CMPB when the timer is decrementing or CMPD when the timer is decrementing (*) Event selected is determined by SOCASELCMP bit. Reserved Reserved SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 818: Event-Trigger Prescale Register (Etps)
R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 819: Event-Trigger Prescale Register (Etps) Field Descriptions
No events have occurred. 1 event has occurred. 2 events have occurred. 3 events have occurred. SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 820: Event-Trigger Interrupt Pre-Scale Register (Etintps)
2 events 0011 3 events 0100 4 events ..1111 15 events C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 821: Event-Trigger Soc Pre-Scale Register (Etsocps)
Generate interrupt on SOCBCNT2 = 4 (fourth event) ..1111 Generate interrupt on SOCBCNT2 = 15 (fifteenth event) SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 822: Event-Trigger Flag Register (Etflg)
If an interrupt is pending, it will not be generated until after the ETFLG[INT] bit is cleared. Refer to Figure 7-44. C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 823: Event-Trigger Clear Register And Mirror Register (Etclr / Etclrm)
Generates an interrupt on EPWMxINT and set the INT flag bit. This bit is used for test purposes. SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 824: Event-Trigger Counter Initialization Control Register (Etcntinitctl)
INTINIT R/W-0:00 R/W-0:00 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 825: Event-Trigger Counter Initialization Register (Etcntinit) Field Descriptions
The ET EPWMxINT counter is initialized with the contents of this register on an ePWM SYNC event or a software force. SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Pulse Width Modulator (ePWM) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 826 6. Clear any spurious ePWM flags (including PIEIFR) 7. Enable ePWM interrupts 8. Enable global interrupts C28 Enhanced Pulse Width Modulator (ePWM) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 827: Spruhe8E - October 2012 - Revised November 2019
Capture Module - Control and Status Registers ..................... Register Mapping ................ Application of the ECAP Module ................Application of the APWM Mode SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 828 Control for continuous time-stamp captures using a 4-deep circular buffer (CAP1-CAP4) scheme • Interrupt capabilities on any of the 4 capture events C28 Enhanced Capture (eCAP) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 829: Capture And Apwm Modes Of Operation
Figure 8-2 further descries the output of the eCAP in APWM mode based on the CMP and PRD values. SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 830: Counter Compare And Prd Effects On The Ecap Output In Apwm Mode
ECAPOUT Off−time Period time Capture Mode Description Figure 8-3 shows the various components that implement the capture function. C28 Enhanced Capture (eCAP) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 831: Capture Function Diagram
This is useful when very high frequency signals are used as inputs. Figure 8-4 shows a functional diagram and Figure 8-5 shows the operation of the prescale function. SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 832: Event Prescale Control
A 2-bit stop register is used to compare the Mod4 counter output, and when equal stops the Mod4 counter and inhibits further loads of the CAP1-CAP4 registers. This occurs during one-shot operation. C28 Enhanced Capture (eCAP) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 833: Details Of The Continuous/One-Shot Block
The 32-bit counter value is captured first, then it is reset to 0 by any of the LD1-LD4 signals. SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 834: Details Of The Counter And Synchronization Block
You can force an interrupt event via the interrupt force register (ECFRC). This is useful for test purposes. C28 Enhanced Capture (eCAP) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 835: Interrupts In Ecap Module
Immediate - APRD or ACMP are transferred to CAP1 or CAP2 immediately upon writing a new value. • On period equal, CTR[31:0] = PRD[31:0] SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 836: Pwm Waveform Details Of Apwm Mode Operation
CMP = PERIOD+1, output low for complete period (100% duty) CMP > PERIOD+1, output low for complete period C28 Enhanced Capture (eCAP) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 837: Time-Base Frequency And Period Calculation
Capture Mode Description www.ti.com Figure 8-10. Time-Base Frequency and Period Calculation CAP1 1 TSCTR SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 838: Time-Stamp Counter Register (Tsctr)
• Software - may be useful for test purposes • APRD shadow register (CAP4) when used in APWM mode C28 Enhanced Capture (eCAP) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 839: Capture-3 Register (Cap3)
Divide by 1 (i.e,. no prescale, by-pass the prescaler) 00001 Divide by 2 00010 Divide by 4 00011 Divide by 6 SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 840: Ecap Control Register 2 (Ecctl2)
R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset C28 Enhanced Capture (eCAP) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 841: Ecap Control Register 2 (Ecctl2) Field Descriptions
Wrap after Capture Event 1 in continuous mode. Stop after Capture Event 2 in one-shot mode Wrap after Capture Event 2 in continuous mode. SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 842 Continuous or one-shot mode control (applicable only in capture mode) Operate in continuous mode Operate in one-Shot mode C28 Enhanced Capture (eCAP) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 843: Ecap Interrupt Enable Register (Eceint)
• Clear spurious eCAP interrupt flags • Enable eCAP interrupts • Start eCAP counter • Enable global interrupts SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 844: Ecap Interrupt Flag Register (Ecflg)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset C28 Enhanced Capture (eCAP) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 845: Ecap Interrupt Forcing Register (Ecfrc)
Force Counter Equal Period Interrupt No effect. Always reads back a 0. Writing a 1 sets the CTR=PRD flag bit. SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 846: Control And Status Register Set
Below are useful #defines which will help in the understanding of the examples. // ECCTL1 (ECAP Control Reg 1) //========================== C28 Enhanced Capture (eCAP) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 847: Capture Sequence For Absolute Time-Stamp And Rising Edge Detect
CAP2 CAP3 CAP4 All capture values valid Polarity selection (can be read) at this time Capture registers [1−4] SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 848 // Calculate 1st period Period2 = TSt3-TSt2; // Calculate 2nd period Period3 = TSt4-TSt3; // Calculate 3rd period C28 Enhanced Capture (eCAP) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 849: Capture Sequence For Absolute Time-Stamp With Rising And Falling Edge Detect
CEVT1 CEVT3 CEVT1 CAPx pin FFFFFFFF CTR[0−31] 00000000 MOD4 CAP1 CAP2 CAP3 CAP4 Polarity selection Capture registers [1−4] SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 850 // Calculate 1st period DutyOnTime1 = TSt2-TSt1; // Calculate On time DutyOffTime1 = TSt3-TSt2; // Calculate Off time C28 Enhanced Capture (eCAP) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 851: Capture Sequence For Delta Mode Time-Stamp And Rising Edge Detect
CAP2 CAP3 CAP4 Polarity selection Capture registers [1−4] All capture values valid (can be read) at this time SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 852 // Fetch Time-Stamp captured at T2 Period2 = ECap1Regs.CAP3; // Fetch Time-Stamp captured at T3 Period3 = ECap1Regs.CAP4; // Fetch Time-Stamp captured at T4 C28 Enhanced Capture (eCAP) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 853: Capture Sequence For Delta Mode Time-Stamp With Rising And Falling Edge Detect
For subsequent compare updates, during run- time, only the shadow registers must be used. SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 854 // Fetch Time-Stamp captured at T4 DutyOffTime2 = ECap1Regs.CAP1; // Fetch Time- Stamp captured at T1 Period1 = DutyOnTime1 + DutyOffTime1; Period2 = DutyOnTime2 + DutyOffTime2; C28 Enhanced Capture (eCAP) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 855: Pwm Waveform Details Of Apwm Mode Operation
// Allow TSCTR to run // Run Time (Instant 1, for example, ISR call) //====================== ECap1Regs.CAP2 = 0x300; SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced Capture (eCAP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 856 // Run Time (Instant 2, for example, another ISR call) //======================\ ECap1Regs.CAP2 = 0x500; // Set Duty cycle, that is, compare value C28 Enhanced Capture (eCAP) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 857 Edge Capture Unit ....................eQEP Watchdog ....................Unit Timer Base ................... eQEP Interrupt Structure ....................eQEP Registers SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced QEP (eQEP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 858: Optical Encoder Disk
166.6 KHz, so by measuring the frequency of either the QEPA or QEPB output, the processor can determine the velocity of the motor. C28 Enhanced QEP (eQEP) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 859: Index Pulse Example
Unit time is basically the inverse of the velocity calculation rate. SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced QEP (eQEP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 860 This signal is typically connected to a sensor or limit switch to notify that the motor has reached a defined position. C28 Enhanced QEP (eQEP) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 861: Functional Block Diagram Of The Eqep Peripheral
0x04 0x00000000 eQEP Maximum Position Count QPOSCMP 0x06 0x00000000 eQEP Position-compare QPOSILAT 0x08 0x00000000 eQEP Index Position Latch SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced QEP (eQEP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 862 QCTMRLAT 0x1F 0x0000 eQEP Capture Timer Latch QCPRDLAT 0x20 0x0000 eQEP Capture Period Latch reserved 0x21 31/0 0x3F C28 Enhanced QEP (eQEP) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 863: Functional Block Diagram Of Decoder Unit
Clock and direction input to position counter is selected using QDECCTL[QSRC] bits, based on interface input requirement as follows: • Quadrature-count mode • Direction-count mode • UP-count mode • DOWN-count mode SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced QEP (eQEP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 864: Quadrature Decoder State Machine
(10) (01) Decrement Decrement counter counter QEPA QEPB Decrement Decrement counter counter eQEP signals Increment Increment counter counter C28 Enhanced QEP (eQEP) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 865: Quadrature-Clock And Direction Decoding
QEPB as a GPIO mux option, or ensure that a signal edge is not generated on the QEPB input. SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced QEP (eQEP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 866 (QEPSTS[FIDF]) in QEPSTS registers, it also remembers the quadrature edge on the first index marker so that same relative quadrature transition is used for index event reset operation. C28 Enhanced QEP (eQEP) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 867: Position Counter Reset By Index Pulse For 1000 Line Encoder (Qposmax = 3999 Or 0Xf9F)
9-9shows the position counter reset operation in this mode. The first index marker fields (QEPSTS[FIDF] and QEPSTS[FIMF]) are not applicable in this mode. SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced QEP (eQEP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 868: Position Counter Underflow/Overflow (Qposmax = 4)
The eQEP index and strobe input can be configured to latch the position counter (QPOSCNT) into QPOSILAT and QPOSSLAT, respectively, on occurrence of a definite event on these pins. C28 Enhanced QEP (eQEP) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 869: Software Index Marker For 1000-Line Encoder (Qepctl[Iel] = 1)
Figure 9-10. Software Index Marker for 1000-line Encoder (QEPCTL[IEL] = 1) QCLK QEPSTS:QDF QPOSCNT Index interrupt/ index event marker QPOSILAT QEPSTS:QDLF SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced QEP (eQEP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 870: Strobe Event Latch (Qepctl[Sel] = 1)
QEPCTL[SWI] bit. This bit is not automatically cleared. While the bit is still set, if a 1 is written to it again, the position counter will be re-initialized. C28 Enhanced QEP (eQEP) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 871: Eqep Position-Compare Unit
Position-Compare Control Register (QPOSCTL) and Table 9-5 describes the QPOSCTL bit fields. SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced QEP (eQEP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 872: Eqep Position-Compare Event Generation Points
( k ) + t ( k ) * t ( k * 1 ) where, C28 Enhanced QEP (eQEP) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 873 QPOSLAT, QCTMRLAT and QCPRDLAT registers, respectively, on unit time out. Figure 9-17 shows the capture unit operation along with the position counter. SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced QEP (eQEP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 874: Eqep Edge Capture Unit
Figure 9-16. Unit Position Event for Low Speed Measurement (QCAPCTL[UPPS] = 0010) QCLK UPEVNT X=N x P N - Number of quadrature periods selected using QCAPCTL[UPPS] bits C28 Enhanced QEP (eQEP) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 875: Eqep Edge Capture Unit - Timing Details
Unit time (T) and unit period(X) are configured using the QUPRD and QCAPCTL[UPPS] registers. Incremental position output and incremental time output is available in the QPOSLAT and QCPRDLAT registers. SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced QEP (eQEP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 876: Eqep Watchdog Timer
Section Section 9.5. Figure 9-19. eQEP Unit Time Base UTIME QEPCTL:UTE SYSCLKOUT QUTMR UTOUT QUPRD QFLG:UTO C28 Enhanced QEP (eQEP) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 877: Eqep Interrupt Generation
DOWN count mode for frequency measurement (QCLK = xCLK, QDIR = 0) SOEN Sync output-enable Disable position-compare sync output Enable position-compare sync output SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced QEP (eQEP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 878: Eqep Control (Qepctl) Register
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset C28 Enhanced QEP (eQEP) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 879: Eqep Control (Qepctl) Register Field Descriptions
The position counter is latched to the QPOSILAT register and the direction flag is latched in the QEPSTS[QDLF] bit. This mode is useful for software index marking. SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced QEP (eQEP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 880: Eqep Position-Compare Control (Qposctl) Register
1 * 4 * SYSCLKOUT cycles 0x001 2 * 4 * SYSCLKOUT cycles 0xFFF 4096 * 4 * SYSCLKOUT cycles C28 Enhanced QEP (eQEP) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 881: Eqep Capture Control (Qcapctl) Register
Figure 9-26. eQEP Position Counter Initialization (QPOSINIT) Register QPOSINIT R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced QEP (eQEP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 882: Eqep Maximum Position Count Register (Qposmax) Register
Figure 9-30. eQEP Strobe Position Latch (QPOSSLAT) Register QPOSSLAT LEGEND: R/W = Read/Write; R = Read only; -n = value after reset C28 Enhanced QEP (eQEP) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 883: Eqep Position Counter Latch (Qposlat) Register
Figure 9-34. eQEP Watchdog Timer (QWDTMR) Register QWDTMR R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced QEP (eQEP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 884: Eqep Watchdog Period (Qwdprd) Register
Interrupt is enabled Position-compare ready interrupt enable Interrupt is disabled Interrupt is enabled Position counter overflow interrupt enable C28 Enhanced QEP (eQEP) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 885: Eqep Interrupt Flag (Qflg) Register
No interrupt generated This bit is set after transferring the shadow register value to the active position compare register. SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced QEP (eQEP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 886: Eqep Interrupt Clear (Qclr) Register
No effect Clears the interrupt flag Clear eQEP compare match event interrupt flag No effect Clears the interrupt flag C28 Enhanced QEP (eQEP) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 887: Eqep Interrupt Force (Qfrc) Register
Force index event latch interrupt No effect Force the interrupt Force strobe event latch interrupt No effect Force the interrupt SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced QEP (eQEP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 888: Eqep Status (Qepsts) Register
Counter-clockwise rotation (or reverse movement) on the first index event Clockwise rotation (or forward movement) on the first index event C28 Enhanced QEP (eQEP) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 889: Eqep Capture Timer (Qctmr) Register
Figure 9-43. eQEP Capture Timer Latch (QCTMRLAT) Register QCTMRLAT LEGEND: R/W = Read/Write; R = Read only; -n = value after reset SPRUHE8E – October 2012 – Revised November 2019 C28 Enhanced QEP (eQEP) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 890: Eqep Capture Period Latch (Qcprdlat) Register
C28 Enhanced QEP (eQEP) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 891 ..............10.2 Analog Common Interface Bus (ACIB) ..............10.3 Analog-to-Digital Converter (ADC) ..................... 10.4 Comparator Block ................10.5 Analog Subsystem Software SPRUHE8E – October 2012 – Revised November 2019 Analog Subsystem Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 892: Analog Subsystem Block Diagram
A simplified model of the ACIB is shown in Figure 10-2 and the signals are defined in Table 10-1. Analog Subsystem SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 893: Simplified Acib Model
ADC trigger and interrupt signals in case of contention. For instances where operations are pending from multiple CPU or DMA sources, the transactions are processed in a round- robin manner. SPRUHE8E – October 2012 – Revised November 2019 Analog Subsystem Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 894: 16-Bit Write
Addr Word Word Bus[7:0] Ready 2-3 Cycle Sync Stall Read Stall Sync Stall Ready 15:8 15:8 Size Digital Buffer Analog Buffer Analog Subsystem SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 895: 32-Bit Read
Analog Buffer Figure 10-8. ADC Trigger Clock Trig Sync Ready 2-3 Cycle Sync Stall Ready Bus[7:0] Stall Size Digital Buffer Analog Buffer SPRUHE8E – October 2012 – Revised November 2019 Analog Subsystem Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 896: Adc Interrupt
8 flexible PIE interrupts total for both ADC modules, can configure interrupt request after any conversion • 8 flexible NVIC interrupts total for both ADC modules, can configure interrupt request after any conversion Analog Subsystem SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 897: Adc Module Block Diagram
The channel and sample window size for SOCx are configured with the CHSEL and ACQPS fields of the ADCSOCxCTL register. SPRUHE8E – October 2012 – Revised November 2019 Analog Subsystem Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 898: Soc Block Diagram
// (ACQPS=6, CHSEL=1, TRIGSEL=5) ADCSOC2CTL = 2846h; // (ACQPS=6, CHSEL=1, TRIGSEL=5) ADCSOC3CTL = 2846h; // (ACQPS=6, CHSEL=1, TRIGSEL=5) TRIG1SEL = 000Bh // (TRIG1SEL=11) Analog Subsystem SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 899: Trigxsel Trigger Options
10001 EPWM5SOCA EPWM5 10010 EPWM5SOCB 10011 EPWM5SYNC 10100 EPWM6SOCA EPWM6 10101 EPWM6SOCB 10110 EPWM6SYNC 10111 EPWM7SOCA EPWM7 11000 EPWM7SOCB 11001 EPWM7SYNC SPRUHE8E – October 2012 – Revised November 2019 Analog Subsystem Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 900: Adcinx Input Model
Switch Resistance (R ): 3.4 k Ω Sampling Capacitor (C ): 1.6 pF Parasitic Capacitance (C ): 5 pF Ω Source Resistance (R ): 50 Analog Subsystem SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 901: Oneshot Single Conversion
2 from the current RR pointer. This is because simultaneous mode will create result for SOCx and SOCx+1, and SOCx+1 will never be triggered by the user. SPRUHE8E – October 2012 – Revised November 2019 Analog Subsystem Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 902 ADCCTL1.RESET bit is set, or when the SOCPRICTL register is written. An example of the round robin priority method is given in Figure 10-14. Analog Subsystem SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 903: Round Robin Priority Example
If two high priority SOC’s are triggered at the same time, the SOC with the lower number will take precedence. SPRUHE8E – October 2012 – Revised November 2019 Analog Subsystem Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 904: High Priority Example
High Priority RRPOINTER RRPOINTER (value = 7) (value = 7) High Priority High Priority RRPOINTER RRPOINTER (value = 7) (value = 12) Analog Subsystem SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 905 There are a total of 8 interrupts available for both ADC1 and ADC2. Each ADC does not have its own set of 8 interrupts. These resources must be shared. SPRUHE8E – October 2012 – Revised November 2019 Analog Subsystem Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 906: Interrupt Structure
NOTE: If the system is reset or the ADC module is reset using Bit 15 (RESET) from the ADC Control Register 1, the Device_cal() routine must be repeated. Analog Subsystem SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 907 Texas Instruments cannot guarantee the parameters specified in the datasheet if a value other than the factory settings contained in the TI reserved OTP memory is written into the ADC trim registers.
Page 908 Digital Value = 4096 [(Input – VREFLO)/(VREFHI – VREFLO)] when VREFLO < Input < VREFHI Digital Value = 4095, when Input ≥ VREFHI *All fractional values are truncated Analog Subsystem SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 909: Adc Registers
The base address of the ADCRESULT registers differs from the base address of the other ADC registers. In the header files, the ADCRESULT registers are found in the AdcResult register file, not AdcRegs. SPRUHE8E – October 2012 – Revised November 2019 Analog Subsystem Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 910: Adc Control Register 1 (Adcctl1) (Address Offset 00H)
Simultaneous Mode: Cleared 14 ADC clocks after negative edge of S/H pulse ADC is available to sample next channel ADC is busy and cannot sample another channel Analog Subsystem SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 911 VREFLO internally connected to the ADC for sampling Reserved Reserved 10.3.11.2 ADC Control Register 2 (ADCCTL2) The register and description are shown below. SPRUHE8E – October 2012 – Revised November 2019 Analog Subsystem Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 912: Adc Control Register 2 (Adcctl2) (Address Offset 01H)
ADCINTFLG flag is set. Both ADCINTFLG and ADCINTOVF flags must be cleared before normal interrupt operation can resume. Analog Subsystem SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 913: Adc Interrupt Flag Clear Register (Adcintflgclr) (Address Offset 05H)
LEGEND: R/W = Read/Write; R = Read only; R-0/W-1 =always read 0, write 1 to set; -n = value after reset SPRUHE8E – October 2012 – Revised November 2019 Analog Subsystem Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 914: Interrupt Select 1 And 2 Register (Intsel1N2) (Address Offset 08H)
R/W-0 Reserved INT7CONT INT7E INT7SEL R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Analog Subsystem SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 915: Interrupt Select 9 And 10 Register (Intsel9N10) (Address Offset 0Ch)
ADCINTx pulses are generated whenever an EOC pulse is generated irrespective if the flag bit is cleared or not. INTxE ADCINTx Interrupt Enable ADCINTx is disabled. ADCINTx is enabled . SPRUHE8E – October 2012 – Revised November 2019 Analog Subsystem Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 916: Adc Start Of Conversion Priority Control Register (Socprictl)
Table 10-13. SOCPRICTL Register Field Descriptions Field Value Description ONESHOT One shot mode disabled One shot mode enabled 14-11 Reserved Reserved Analog Subsystem SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 917 SOC0-SOC14 are high priority, SOC15 is in round robin mode. All SOCs are in high priority mode, arbitrated by SOC number Others Invalid selection. SPRUHE8E – October 2012 – Revised November 2019 Analog Subsystem Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 918: Adc Sample Mode Register (Adcsamplemode) (Address Offset 12H)
EOC8 and EOC9 associated with SOC8 and SOC9 pair. SOC8’s and SOC9’s results will be placed in ADCRESULT8 and ADCRESULT9 registers, respectively. Analog Subsystem SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 919: Adc Interrupt Trigger Soc Select 1 Register (Adcintsocsel1) (Address Offset 14H)
No ADCINT will trigger SOCx. TRIGSEL field determines SOCx trigger. ADCINT1 will trigger SOCx. TRIGSEL field is ignored. ADCINT2 will trigger SOCx. TRIGSEL field is ignored. Invalid selection. SPRUHE8E – October 2012 – Revised November 2019 Analog Subsystem Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 920: Adc Interrupt Trigger Soc Select 2 Register (Adcintsocsel2) (Address Offset 15H)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Analog Subsystem SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 921: Adc Soc Overflow 1 Register (Adcsocovf1) (Address Offset 1Ch)
ADCSOCOVF1 register, then hardware has priority and the ADCSOCOVF1 bit will be set. NOTE: The following ADC SOC0 - SOC15 Control Registers are EALLOW protected. SPRUHE8E – October 2012 – Revised November 2019 Analog Subsystem Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 922: Adc Soc0 - Soc15 Control Registers (Adcsocxctl) (Address Offset 20H - 2Fh)
ADCTRIG5 – ADC Trigger 5 ADCTRIG6 – ADC Trigger 6 ADCTRIG7 – ADC Trigger 7 ADCTRIG8 – ADC Trigger 8 Others Invalid selection. Reserved Reserved Analog Subsystem SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 923 ADCINA5/ADCINB5 pair ADCINA6/ADCINB6 pair ADCINA7/ADCINB7 pair Invalid selection. Invalid selection. Invalid selection. Invalid selection. Invalid selection. Invalid selection. Invalid selection. Invalid selection. SPRUHE8E – October 2012 – Revised November 2019 Analog Subsystem Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 924: Adc Reference/Gain Trim Register (Adcreftrim) (Address Offset 40H)
Figure 10-38. ADC Offset Trim Register (ADCOFFTRIM) (Address Offset 41h) Reserved OFFTRIM R/W-0 LEGEND: R/W = Read/Write; R = Read only; -n = value after reset Analog Subsystem SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 925: Adc Revision Register (Adcrev) (Address Offset 4Fh)
SOC4, the completed results of those conversions will be placed in ADCRESULT4 and ADCRESULT5. See 1.11 for timings of when this register is written. SPRUHE8E – October 2012 – Revised November 2019 Analog Subsystem Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 926: Analog Subsystem Control Registers (Analogsysctrlreg)
The reset source for this register is shared resources reset. Analog Subsystem SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 927: Adc Interrupt Overflow Detect Register (Intovf)
No overflow. Overflow detected. ADCINT2 ADCINT2 Overflow Flag Status No overflow. Overflow detected. ADCINT1 ADCINT1 Overflow Flag Status No overflow. Overflow detected. SPRUHE8E – October 2012 – Revised November 2019 Analog Subsystem Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 928: Adc Interrupt Overflow Clear Register (Intovfclr)
Clears overflow flag. ADCINT2 ADCINT2 Overflow Flag Clear No action. Clears overflow flag. ADCINT1 ADCINT1 Overflow Flag Clear No action. Clears overflow flag. Analog Subsystem SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 929: Control System: Lock Register (Clock)
This bit, if written simultaneously with the correct PSWD value, will enable write protection for the CLKDIV bits in the CCLKCTL register. Write protection can only be disabled by a system reset. Reserved Reserved SPRUHE8E – October 2012 – Revised November 2019 Analog Subsystem Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 930: Control System: Acib Status Register (Ccibstatus)
Reads of this bit will give the current state of the READY signal. APGOODSTS Analog Subsystem Power Good Status Power not present Power present Analog Subsystem SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 931: Control System: Clock Control Register (Cclkctl)
Clock is turned off. Divide by /1 mode Divide by /2 mode (Default) Divide by /4 mode Divide by /8 mode Reserved Reserved Reserved SPRUHE8E – October 2012 – Revised November 2019 Analog Subsystem Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 932: Adc Start Of Conversion Trigger Overflow Detect Register (Trigovf)
Indicates if overflow occurred on respective ADC trigger. No overflow. Overflow detected. TRIG1 Indicates if overflow occurred on respective ADC trigger. No overflow. Overflow detected. Analog Subsystem SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 933: Adc Start Of Conversion Trigger Overflow Flag Clear Register (Trigovfclr)
Clears ADC trigger overflow flag in TRIGOVF register. No action. Clears overflow flag. TRIG1 Clears ADC trigger overflow flag in TRIGOVF register. No action. Clears overflow flag. SPRUHE8E – October 2012 – Revised November 2019 Analog Subsystem Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 934: Adc Start Of Conversion Trigx Input Select Register (Trigxsel)
11001 EPWM7SYNC (EPWM7) 11010 EPWM8SOCA (EPWM8) 11011 EPWM8SOCB (EPWM8) 11100 EPWM8SYNC (EPWM8) 11101 EPWM9SOCA (EPWM9) 11110 EPWM9SOCB (EPWM9) 11111 EPWM9SYNC (EPWM9) Analog Subsystem SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 935: Timing Example For Sequential Mode / Late Interrupt Pulse
Result 0 latched on this cycle does not include the additional cycles required for the C28x and M3 subsystems to read the ADC result registers using the ACIB. SPRUHE8E – October 2012 – Revised November 2019 Analog Subsystem Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 936: Timing Example For Sequential Mode / Early Interrupt Pulse
Result 0 latched on this cycle does not include the additional cycles required for the C28x and M3 subsystems to read the ADC result registers using the ACIB. Analog Subsystem SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 937: Timing Example For Simultaneous Mode / Late Interrupt Pulse
Result 0 (A) and Result 0 (B) latched on their respective cycles does not include the additional cycles required for the C28x and M3 subsystems to read the ADC result registers using the ACIB. SPRUHE8E – October 2012 – Revised November 2019 Analog Subsystem Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 938: Timing Example For Simultaneous Mode / Early Interrupt Pulse
The comparator output can be externally connected to a GPIO in order to connect to an ePWM Trip Zone module. Analog Subsystem SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 939: Comparator Block Diagram
(B side input) of the comparator. The voltage output of the DAC is controlled by the DACVAL bit field in the DACVAL register. The output of the DAC is given by the equation: SPRUHE8E – October 2012 – Revised November 2019 Analog Subsystem Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 940 QUALSEL bit field. NOTE: Some downstream modules (such as the ePWM DC Submodule) may require a minimum comparator output pulse-width for correct operation. Analog Subsystem SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 941: Comparator Control (Compctl) Register
Synchronization select for output of the comparator before being passed to ETPWM/GPIO blocks Asynchronous version of Comparator output is passed Synchronous version of comparator output is passed SPRUHE8E – October 2012 – Revised November 2019 Analog Subsystem Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 942: Compare Output Status (Compsts) Register
Field Value Description 15-10 Reserved Reserved DACVAL 0-3FFh DAC Value bits, scales the output of the DAC from 0 – 1023. Analog Subsystem SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 943: Dac Test (Dactest) Register
NOTE: The maximum clock frequency for the Analog Subsystem clock is 37.5 MHz. This function is successful if it returns a value of 0xA005. SPRUHE8E – October 2012 – Revised November 2019 Analog Subsystem Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 944 2 registers. These are the registers written to using the AnalogClockEnable and AnalogClockDisable functions. Valid #define values for the AnalogConfigReg parameter are located in the F28M35x_AnalogSysCtrl_defines.h file. Analog Subsystem SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 945 Choose Analog Config Register 2 (used to enable ADC2, COMP1,2,3,4,5,6) Valid #define values for the AnalogClockMask parameter are located in the sysctl.h file. SPRUHE8E – October 2012 – Revised November 2019 Analog Subsystem Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 946 ADC1, ADC2, COMP1, and COMP4 analog peripherals. The example also reads the status of the Analog Subsystem Config Registers to check for correctness. Analog Subsystem SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 947 Config 1 and Analog Config 2 Registers if the header file functions (InitSysCtrl, InitAdc1, and InitAdc2) are not used to enable ADC1 or ADC2. SPRUHE8E – October 2012 – Revised November 2019 Analog Subsystem Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 948 Channel Priority ..............11.6 Address Pointer and Transfer Control ................. 11.7 Overrun Detection Feature ..................11.8 Register Descriptions C28 Direct Memory Access (DMA) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 949 Throughput: 4 cycles/word (5 cycles/word for McBSP reads) 11.2 Architecture 11.2.1 Block Diagram Figure 11-1 shows a device-level block diagram of the DMA. SPRUHE8E – October 2012 – Revised November 2019 C28 Direct Memory Access (DMA) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 950: Dma Block Diagram
CONTROL.CHx[PERINTFRC] bit. Likewise, software can always clear a pending DMA trigger using the CONTROL.CHx[PERINTCLR] bit. C28 Direct Memory Access (DMA) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 951: Peripheral Interrupt Trigger Input Diagram
Table 11-1 shows the interrupt trigger source options that are available for each channel. SPRUHE8E – October 2012 – Revised November 2019 C28 Direct Memory Access (DMA) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 952: Peripheral Interrupt Trigger Source Options
ADC 2 memory-mapped result registers • McBSP data receive registers (DRR2/DRR1) and data transmit registers (DXR2/DXR1) • ePWM1-9/HRPWM1-8 registers C28 Direct Memory Access (DMA) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 953: 4-Stage Pipeline Dma Transfer
If instead the channel were configured to transfer the same amount of data 32 bits at a time (the word size is configured to 32 bits) the transfer would take: SPRUHE8E – October 2012 – Revised November 2019 C28 Direct Memory Access (DMA) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 954 DMA access to that same interface has priority over the pending CPU access when the current CPU access completes. C28 Direct Memory Access (DMA) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 955: Arbitration When Accessing Acib
In this mode, all channels have equal priority and each enabled channel is serviced in round-robin fashion as follows: SPRUHE8E – October 2012 – Revised November 2019 C28 Direct Memory Access (DMA) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 956 Typically Channel 1 would be used in this mode for the ADC, since its data rate is so high. However, Channel 1 High Priority Mode may be used in conjunction with any peripheral. C28 Direct Memory Access (DMA) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 957 Source/Destination Begin Address Pointers (SRC/DST_BEG_ADDR)— This is the wrap pointer. SPRUHE8E – October 2012 – Revised November 2019 C28 Direct Memory Access (DMA) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 958 This value is a signed 2's compliment number so that the address pointer can be incremented or decremented as required. C28 Direct Memory Access (DMA) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 959 All of the above features and modes are shown in Figure 11-6. SPRUHE8E – October 2012 – Revised November 2019 C28 Direct Memory Access (DMA) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 960: Dma State Diagram
Generate DMACHx interrupt CHINTMODE CONTINUOUS to CPU at end of == 1 == 1 transfer (if enabled) C28 Direct Memory Access (DMA) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 961 11-7. If the overrun interrupt is enabled then the channel interrupt will be generated to the PIE module. SPRUHE8E – October 2012 – Revised November 2019 C28 Direct Memory Access (DMA) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 962: Overrun Detection Logic
CONTROL.CHx CONTROL.CHx [PERINTFLG] MODE.CHx [OVRFLG] [CHINTE] PERx_INT Latch CONTROL.CHx MODE.CHx [ERRCLR] [OVERNITE] C28 Direct Memory Access (DMA) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 963: Dma Register Summary
Shadow Destination Begin and Current Address Pointer Section Registers 11.8.21 All DMA register writes are EALLOW protected. SPRUHE8E – October 2012 – Revised November 2019 C28 Direct Memory Access (DMA) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 964: Dma Control Register (Dmactrl)
In case CH1 is high priority, the state machine restarts from CH2 (or the next highest enabled channel). C28 Direct Memory Access (DMA) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 965 (i.e., a NOP instruction) after writing to this bit should be introduced before attempting an access to any other DMA register. SPRUHE8E – October 2012 – Revised November 2019 C28 Direct Memory Access (DMA) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 966: Debug Control Register (Debugctrl)
DMA Silicon Revision Bits: These bits specify the DMA revision and are changed if any bug fixes are performed. 0x0000 First release C28 Direct Memory Access (DMA) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 967: Priority Control Register 1 (Priorityctrl1)
Channel priority can only be changed when all channels are disabled. A priority reset should be performed before restarting channels after changing priority. SPRUHE8E – October 2012 – Revised November 2019 C28 Direct Memory Access (DMA) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 968: Priority Status Register (Prioritystat)
CH 1 0,1,0 CH 2 0,1,1 CH 3 1,0,0 CH 4 1,0,1 CH 5 1,1,0 CH 6 C28 Direct Memory Access (DMA) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 969: Mode Register (Mode)
The PERINTFLG being set indicates a previous peripheral event is latched and has not been serviced by the DMA. Reserved Reserved SPRUHE8E – October 2012 – Revised November 2019 C28 Direct Memory Access (DMA) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 970 None ePWM5SOCA None ePWM5 ePWM5SOCB None ePWM6SOCA None ePWM6 ePWM6SOCB None ePWM7SOCA None ePWM7 ePWM7SOCB None C28 Direct Memory Access (DMA) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 971: Control Register (Control)
ADC or overrun has priority and the SYNCERR or OVRFLG bit is set. Reserved Reserved SPRUHE8E – October 2012 – Revised November 2019 C28 Direct Memory Access (DMA) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 972 DMA channel out of a HALT condition See Figure 11-6 for the various positions the state machine can be at when HALTED. C28 Direct Memory Access (DMA) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 973: Burst Size Register (Burst_Size)
31 words left in a burst The above values represent the state of the counter at the HALT conditions. SPRUHE8E – October 2012 – Revised November 2019 C28 Direct Memory Access (DMA) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 974: Source Burst Step Size Register (Src_Burst_Step)
Sub 2 from address 0xF000 Sub 4096 from address Only values from -4096 to 4095 are valid. C28 Direct Memory Access (DMA) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 975: Destination Burst Step Register Size (Dst_Burst_Step)
These bits specify the number of bursts to transfer: 0x0000 Transfer 1 burst 0x0001 Transfer 2 bursts 0x0002 Transfer 3 bursts 0xFFFF Transfer 65536 bursts SPRUHE8E – October 2012 – Revised November 2019 C28 Direct Memory Access (DMA) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 976: Transfer Count Register (Transfer_Count)
Sub 2 from address 0xF000 Sub 4096 from address Only values from -4096 to 4095 are valid. C28 Direct Memory Access (DMA) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 977: Destination Transfer Step Size Register (Dst_Transfer_Step)
To disable the wrap function, set the WRAPSIZE bit field to a number larger than the TRANSFERSIZE bit field. SPRUHE8E – October 2012 – Revised November 2019 C28 Direct Memory Access (DMA) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 978: Source/Destination Wrap Step Size Registers (Src/Dst_Wrap_Step) - Eallow Protected
Sub 2 from address 0xF000 Sub 4096 from address Only values from -4096 to 4095 are valid. C28 Direct Memory Access (DMA) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 979: Shadow Source Begin And Current Address Pointer Registers (Src_Beg_Addr_Shadow/Dst_Beg_Addr_Shadow) - All Eallow Protected
Table 11-22. Active Source Begin and Current Address Pointer Registers (SRC_BEG_ADDR/DST_BEG_ADDR) Field Descriptions Field Value Description 31-22 Reserved Reserved 21-0 BEGADDR 22-bit address value SPRUHE8E – October 2012 – Revised November 2019 C28 Direct Memory Access (DMA) Module Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 980: Shadow Destination Begin And Current Address Pointer Registers (Src_Addr_Shadow/Dst_Addr_Shadow) - All Eallow Protected
Table 11-24. Active Destination Begin and Current Address Pointer Registers (SRC_ADDR/DST_ADDR) Field Descriptions Field Value Description 31-22 Reserved Reserved 21-0 ADDR 22-bit address value C28 Direct Memory Access (DMA) Module SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 981: C28 Serial Peripheral Interface (Spi)
Enhanced SPI Module Overview ............. 12.2 C28 SPI-A to M3 SSI3 Internal Loopback ................12.3 SPI Registers and Waveforms 1001 SPRUHE8E – October 2012 – Revised November 2019 C28 Serial Peripheral Interface (SPI) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 982: Enhanced Spi Module Overview
Simultaneous receive and transmit operation (transmit function can be disabled in software) • Transmitter and receiver operations are accomplished through either interrupt- driven or polled algorithms. C28 Serial Peripheral Interface (SPI) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 983: Spi Block Diagram
SPI in slave mode, showing the basic control blocks available on the SPI module. SPRUHE8E – October 2012 – Revised November 2019 C28 Serial Peripheral Interface (SPI) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 984: Serial Peripheral Interface Module Block Diagram
LSPCLK SPICCR.6 SPICTL.3 SPICLK SPIBRR.6 − 0 SPISTE of a slave device is driven low by the master. C28 Serial Peripheral Interface (SPI) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 985: Spi Module Signal Summary
SPICCR (SPI configuration control register). Contains control bits used for SPI configuration – SPI module software reset – SPICLK polarity selection – Four SPI character-length control bits SPRUHE8E – October 2012 – Revised November 2019 C28 Serial Peripheral Interface (SPI) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 986: Spi Operation
The master can initiate data transfer at any time because it controls the SPICLK signal. The software, however, determines how the master detects when the slave is ready to broadcast data. C28 Serial Peripheral Interface (SPI) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 987: Spi Master/Slave Connection
The transfer rate is defined by this clock. The SPICLK input frequency should be no greater than the LSPCLK frequency divided by 4. SPRUHE8E – October 2012 – Revised November 2019 C28 Serial Peripheral Interface (SPI) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 988: Spi Interrupts
If the CPU does not read the character by the time the next complete character has been received, the new character is written into SPIRXBUF, and the RECEIVER OVERRUN Flag bit (SPISTS.7) is set. C28 Serial Peripheral Interface (SPI) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 989 = 1 if SPISOMI data is high; x = 0 if SPISOMI data is low; master mode is assumed. SPRUHE8E – October 2012 – Revised November 2019 C28 Serial Peripheral Interface (SPI) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 990 Rising Edge With Delay. The SPI transmits data one half-cycle ahead of the rising edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal. C28 Serial Peripheral Interface (SPI) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 991: Spiclk Signal Options
Figure 12-5. SPI: SPICLK-CLKOUT Characteristic When (BRR + 1) is Odd, BRR > 3, and CLOCK POLARITY = 1 2 cycles 3 cycles 2 cycles CLKOUT SPICLK SPRUHE8E – October 2012 – Revised November 2019 C28 Serial Peripheral Interface (SPI) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 992 (CLOCK POLARITY = 0) or during the high pulse (CLOCK POLARITY = 1) of the SPICLK. Figure 12-6 is applicable for 8-bit word length transmissions. The figure is shown for illustrative purposes only. C28 Serial Peripheral Interface (SPI) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 993: Spi Fifo Description
SPI will be disabled and this interrupt will service as SPI receive FIFO interrupt. 6. Buffers. Transmit and receive buffers are supplemented with two 4x16 FIFOs. The one-word transmit SPRUHE8E – October 2012 – Revised November 2019 C28 Serial Peripheral Interface (SPI) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 994: Spi Fifo Interrupt Flags And Enable Logic Generation
SPIRXINT Transmit empty SPIINT SPIINTENA SPIRXINT In non FIFO mode, SPIRXINT is the same as the SPIINT interrupt. C28 Serial Peripheral Interface (SPI) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 995: Spi 3-Wire Mode Description
Figure 12-8. SPI 3-wire Master Mode GPIO MUX SPI Module Data RX SPIDAT Free pin Data TX SPIMOMIx Talk SPICTL.1 SPRUHE8E – October 2012 – Revised November 2019 C28 Serial Peripheral Interface (SPI) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 996: Spi 3-Wire Slave Mode
!=1) {} // Waits until data rx’d dummy = SpiaRegs.SPIRXBUF; // Clears junk data from itself // bc it rx’d same data tx’d C28 Serial Peripheral Interface (SPI) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 997: Spi Steinv Bit In Digital Audio Transfers
SPI modules can be connected as shown in Figure 12-10. SPRUHE8E – October 2012 – Revised November 2019 C28 Serial Peripheral Interface (SPI) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 998: C28 Spi-A To M3 Ssi3 Internal Loopback
M3 SSI3 and C28 SPI-A. The internal connection logic block handles the signal routing between the peripherals and the GPIO mux. C28 Serial Peripheral Interface (SPI) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 999: Loopback Initialization And Configuration
3. Enable and configure the C28 SPI module as detailed in Section 12.1.5.4. To enable M3 SSI3 slave to C28 SPI-A master loopback mode, perform the following steps: SPRUHE8E – October 2012 – Revised November 2019 C28 Serial Peripheral Interface (SPI) Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...
Page 1000 CPHA bits are different from the C28 CPOL and CPHA bits. Using incompatible configurations can cause data to be shifted by one bit. 1000 C28 Serial Peripheral Interface (SPI) SPRUHE8E – October 2012 – Revised November 2019 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated...

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Texas Instruments Concerto F28M36 Series Technical Reference Manual

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