Epi General-Purpose Configuration (Epigpcfg) Register, Offset 0X010; Epi General-Purpose Configuration (Epigpcfg) Register [Offset 0X010]; Epi General-Purpose Configuration (Epigpcfg) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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17.11.7 EPI General-Purpose Configuration (EPIGPCFG) Register, offset 0x010

NOTE: The MODE field in the EPICFG register determines which configuration register is accessed

for offsets 0x010 and 0x014.

To access EPIGPCFG, the MODE field must be 0x0.

The RD2CYC bit must be set at all times in General-Purpose mode to ensure proper

The General-Purpose configuration register is used to configure the control, data, and address pins. This

mode can be used for custom interfaces with FPGAs, CPLDs, and for digital data acquisition and actuator

control. Note that this register is reset when the MODE field in the EPICFG register is changed. If another

mode is selected and the General-purpose mode is selected again, the register the values must be

reinitialized.

This mode is designed for three general types of use:

Extremely high-speed clocked interfaces to FPGAs and CPLDs, with three sizes of data and optional

addresses. Framing and clock-enable permit more optimized interfaces.

General parallel GPIO. From 1 to 32 pins may be written or read, with the speed precisely controlled

by the baud rate in the EPIBAUD register (when used with the NBRFIFO and/or the WFIFO) or by rate

of accesses from software or µDMA.

General custom interfaces of any speed.

The configuration allows for choice of an output clock(free running or gated), a framing signal (with frame

size),a ready input (to stretch transactions), read and write strobes, address of varying sizes, and data of

varying sizes. Additionally, provisions are made for splitting address and data phases on the external

Figure 17-34. EPI General-Purpose Configuration (EPIGPCFG) Register [offset 0x010]

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 17-20. EPI General-Purpose Configuration (EPIGPCFG) Register Field Descriptions

SPRUHE8E – October 2012 – Revised November 2019

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The EPI clock is generated from the COUNT0 field in the EPIBAUD register (as is the system clock

which is divided down from it).

Note: If general purpose mode is configured to 32-bit data transfers (DSIZE = 0x3 in the EPICFG

No clock output.

EPI0S31 functions as the EPI clock output.

Note that EPI0S27 is an iRDY signal if RDYEN is set. CLKGATE is ignored if CLKPIN is 0 or if the

COUNT0 field in the EPIBAUD register is cleared.

The EPI clock is free running.

The EPI clock is output only when there is data to write or read (current transaction); otherwise the

EPI clock is held low.

External Peripheral Interface (EPI)

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