Gptm Timer A Interval Load (Gptmtailr) Register; Gptm Timer A Interval Load (Gptmtbilr) Register; Gptm Timer A Interval Load (Gptmtailr) Register Field Descriptions; Gptm Timer A Interval Load (Gptmtbilr) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

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LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 2-13. GPTM Timer A Interval Load (GPTMTAILR) Register Field Descriptions

2.6.10 GPTM Timer B Interval Load (GPTMTBILR) Register, offset 0x02C

The GPTM Timer B Interval Load (GPTMTBILR) register is used to load the starting count value into the

timer, when the timer is counting down . When the timer is counting up, this register sets the upper bound

for the timeout event.

When a GPTM is configured to one of the 32-bit modes, the contents of bits 15:0 in this register are

loaded into the upper 16 bits of the GPTMTAILR register. Reads from this register return the current value

of Timer B and writes are ignored. In a 16-bit mode, bits 15:0 are used for the load value. Bits 31:16 are

reserved in both cases.

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 2-14. GPTM Timer A Interval Load (GPTMTBILR) Register Field Descriptions

2.6.11 GPTM Timer A Match (GPTMTAMATCHR) Register, offset 0x030

The GPTM Timer A Match (GPTMTAMATCHR) register is loaded with a match value. Interrupts can be

generated when the timer value is equal to the value in this register in one-shot or periodic mode.

In Edge-Count mode, this register along with GPTMTAILR, determines how many edge events are

counted. The total number of edge events counted is equal to the value in GPTMTAILR minus this value.

In PWM mode, this value along with GPTMTAILR, determines the duty cycle of the output PWM signal.

When a GPTM is configured to one of the 32-bit modes, GPTMTAMATCHR appears as a 32-bit register

(the upper 16-bits correspond to the contents of the GPTM Timer B Match (GPTMTBMATCHR) register).

In a 16-bit mode, the upper 16 bits of this register read as 0s and have no effect on the state of

GPTMTBMATCHR.

SPRUHE8E – October 2012 – Revised November 2019

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Figure 2-14. GPTM Timer A Interval Load (GPTMTAILR) Register

GPTM Timer A Interval Load Register

Writing this field loads the counter for Timer A. A read returns the current value of GPTMTAILR.

Figure 2-15. GPTM Timer A Interval Load (GPTMTBILR) Register

GPTM Timer B Interval Load Register

Writing this field loads the counter for Timer B. A read returns the current value of GPTMTBILR.

When a GPTM is in 32-bit mode, writes are ignored, and reads return the current value of

M3 General-Purpose Timers

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