M3Nmi Flag Force (Mnmiflgfrc) Register; M3Nmi Flag Force (Mnmiflgfrc) Register Field Descriptions - Texas Instruments Concerto F28M36 Series Technical Reference Manual

www.ti.com
Table 1-74. M3NMI Flag Clear (MNMIFLGCLR) Register Field Descriptions (continued)
Bit Field
4 M3BISTERR
3-2 Reserved
1 CLOCKFAIL
0 NMIINT

1.13.5.4 M3NMI Flag Force (MNMIFLGFRC) Register

31
15
7 6
C28PIENMIERR EXTGPIO
R/W-0 R/W-0
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset
Table 1-75. M3NMI Flag Force (MNMIFLGFRC) Register Field Descriptions
Bit Field
31-10 Reserved
9 ACIBERR
8 C28NMIWDRST
7 C28PIENMIERR
6 EXTGPIO
5 C28BISTERR
SPRUHE8E – October 2012 – Revised November 2019
Submit Documentation Feedback
Value Description
M3 BIST Error Flag
0 Writes of 0 are ignored. Always reads back 0.
1 Writing a 1 to the respective bit clears the corresponding flag bit in the NMIFLG and NMISHDFLG
registers.
Note 1: If hardware is trying to set a bit to 1 while software is trying to clear a bit to 0 on the same
cycle, hardware has priority.
Note 2: Users should clear the pending FAIL flag first and then clear the NMIINT flag.
Reserved
Clock Fail NMI Flag Clear
0 Ignored; always reads back 0.
1 Clears the corresponding flag bit in the NMIFLG register.
NMI Interrupt Flag Clear
0 Ignored; always reads back 0.
1 Clears the corresponding flag bit in the NMIFLG register.
Figure 1-64. M3NMI Flag Force (MNMIFLGFRC) Register
Reserved
R-0
5 4
C28BISTERR M3BISTERR
R/W-0 R/W-0
Value Description
Reserved
CIB Error NMI Flag Force
0 Ignored; always reads back 0. This can be used as a means to test the NMI mechanisms.
1 Sets the corresponding flag bit in the NMIFLG register.
C28 NMI WD Reset Flag Force
0 Ignored; always reads back 0. This can be used as a means to test the NMI mechanisms.
1 Sets the corresponding flag bit in the NMIFLG register.
C28 PIE NMIERR NMI Flag Force
0 Ignored; always reads back 0. This can be used as a means to test the NMI mechanisms.
1 Sets the corresponding flag bit in the NMIFLG register.
External GPIO NMI Flag Force
0 Ignored; always reads back 0. This can be used as a means to test the NMI mechanisms.
1 Sets the corresponding flag bit in the NMIFLG register.
C28 BIST Error Flag
0 Writes of 0 are ignored. Always reads back 0. This can be used as a means to test the NMI
mechanisms.
1 Writing a 1 to these bits will set the respective FAIL flag in the NMIFLG and NMISHDFLG registers.
Copyright © 2012–2019, Texas Instruments Incorporated
Reserved
R-0:0
10
3 2
Reserved
R-0:0
System Control Registers
9 8
ACIBERR C28NMIWDRST
R/W-0 R/W-0
1 0
CLOCKFAIL Reserved
R/W-0 R-0
System Control and Interrupts
16
205